Let isRead be true for store-conditional
This works around a deadlock bug in the L1 D$, and is arguably true.
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@ -43,7 +43,7 @@ trait MemoryOpConstants {
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def isAMO(cmd: UInt) = cmd(3) || cmd === M_XA_SWAP
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def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
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def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || isAMO(cmd)
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def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd)
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def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd)
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def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
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}
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