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removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants

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This commit is contained in:
Henry Cook 2014-04-01 17:14:45 -07:00
parent fbca7c6bb3
commit b1df49ba30
5 changed files with 16 additions and 42 deletions
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28
uncore/src/main/scala/consts.scala
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@ -2,7 +2,6 @@ package uncore
package constants
import Chisel._
import scala.math.max
object MemoryOpConstants extends MemoryOpConstants
trait MemoryOpConstants {
@ -43,30 +42,3 @@ trait MemoryOpConstants {
def isWrite(cmd: Bits) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: Bits) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
object AddressConstants extends AddressConstants
trait AddressConstants {
val PADDR_BITS = 32
val VADDR_BITS = 43;
val PGIDX_BITS = 13;
val PPN_BITS = PADDR_BITS-PGIDX_BITS;
val VPN_BITS = VADDR_BITS-PGIDX_BITS;
val ASID_BITS = 7;
val PERM_BITS = 6;
}
object CacheConstants extends CacheConstants
trait CacheConstants {
val CACHE_DATA_SIZE_IN_BYTES = 1 << 6
val OFFSET_BITS = log2Up(CACHE_DATA_SIZE_IN_BYTES)
}
trait TileLinkSizeConstants {
val ACQUIRE_WRITE_MASK_BITS = 6
val ACQUIRE_SUBWORD_ADDR_BITS = 3
val ACQUIRE_ATOMIC_OP_BITS = 4
}
trait MemoryInterfaceConstants extends
CacheConstants with
AddressConstants

10
uncore/src/main/scala/htif.scala
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@ -41,7 +41,7 @@ class SCRIO(n: Int) extends Bundle
val wdata = Bits(OUTPUT, 64)
}
class HTIF(w: Int, pcr_RESET: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extends Module
class HTIF(w: Int, pcr_RESET: Int, nSCR: Int, offsetBits: Int)(implicit conf: TileLinkConfiguration) extends Module
{
implicit val (ln, co) = (conf.ln, conf.co)
val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client
@ -75,7 +75,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int)(implicit conf: TileLinkConfigurati
when (rx_count === UInt(short_request_bits/w-1)) {
cmd := next_cmd
size := rx_shifter_in(15,4)
pos := rx_shifter_in(15,4+OFFSET_BITS-3)
pos := rx_shifter_in(15,4+offsetBits-3)
seqno := rx_shifter_in(23,16)
addr := rx_shifter_in(63,24)
}
@ -95,7 +95,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int)(implicit conf: TileLinkConfigurati
val pcr_coreid = addr(log2Up(nTiles)-1+20+1,20)
val pcr_wdata = packet_ram(0)
val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
val bad_mem_packet = size(offsetBits-1-3,0).orR || addr(offsetBits-1-3,0).orR
val nack = Mux(cmd === cmd_readmem || cmd === cmd_writemem, bad_mem_packet,
Mux(cmd === cmd_readcr || cmd === cmd_writecr, size != UInt(1),
Bool(true)))
@ -157,7 +157,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int)(implicit conf: TileLinkConfigurati
when (state === state_mem_finish && io.mem.grant_ack.ready) {
state := Mux(cmd === cmd_readmem || pos === UInt(1), state_tx, state_rx)
pos := pos - UInt(1)
addr := addr + UInt(1 << OFFSET_BITS-3)
addr := addr + UInt(1 << offsetBits-3)
}
when (state === state_tx && tx_done) {
when (tx_word_count === tx_size) {
@ -176,7 +176,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int)(implicit conf: TileLinkConfigurati
mem_req_data = Cat(packet_ram(idx), mem_req_data)
}
acq_q.io.enq.valid := state === state_mem_rreq || state === state_mem_wreq
val init_addr = addr.toUInt >> UInt(OFFSET_BITS-3)
val init_addr = addr.toUInt >> UInt(offsetBits-3)
acq_q.io.enq.bits := Mux(cmd === cmd_writemem,
Acquire(co.getUncachedWriteAcquireType, init_addr, UInt(0)),
Acquire(co.getUncachedReadAcquireType, init_addr, UInt(0)))

5
uncore/src/main/scala/memserdes.scala
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@ -2,6 +2,11 @@ package uncore
import Chisel._
import scala.math._
case class AddressSpaceConfiguration(paddrBits: Int, vaddrBits: Int, pgIdxBits: Int, asidBits: Int, permBits:Int) {
val ppnBits = paddrBits - pgIdxBits
val vpnBits = vaddrBits - pgIdxBits
}
case class MemoryIFConfiguration(addrBits: Int, dataBits: Int, tagBits: Int, dataBeats: Int)
abstract trait MemoryIFSubBundle extends Bundle {

5
uncore/src/main/scala/package.scala
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@ -1,7 +1,4 @@
package object uncore extends
uncore.constants.MemoryOpConstants with
uncore.constants.TileLinkSizeConstants with
uncore.constants.MemoryInterfaceConstants
package object uncore extends uncore.constants.MemoryOpConstants
{
implicit def toOption[A](a: A) = Option(a)
}

10
uncore/src/main/scala/tilelink.scala
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@ -1,7 +1,7 @@
package uncore
import Chisel._
case class TileLinkConfiguration(co: CoherencePolicyWithUncached, ln: LogicalNetworkConfiguration, masterXactIdBits: Int, clientXactIdBits: Int, dataBits: Int)
case class TileLinkConfiguration(co: CoherencePolicyWithUncached, ln: LogicalNetworkConfiguration, addrBits: Int, masterXactIdBits: Int, clientXactIdBits: Int, dataBits: Int, writeMaskBits: Int, wordAddrBits: Int, atomicOpBits: Int)
abstract trait TileLinkSubBundle extends Bundle {
implicit val conf: TileLinkConfiguration
@ -9,7 +9,7 @@ abstract trait TileLinkSubBundle extends Bundle {
}
trait HasPhysicalAddress extends TileLinkSubBundle {
val addr = UInt(width = PADDR_BITS - OFFSET_BITS)
val addr = UInt(width = conf.addrBits)
}
trait HasClientTransactionId extends TileLinkSubBundle {
@ -69,9 +69,9 @@ class Acquire(implicit val conf: TileLinkConfiguration) extends ClientSourcedMes
with HasClientTransactionId
with HasTileLinkData {
val a_type = UInt(width = conf.co.acquireTypeWidth)
val write_mask = Bits(width = ACQUIRE_WRITE_MASK_BITS)
val subword_addr = Bits(width = ACQUIRE_SUBWORD_ADDR_BITS)
val atomic_opcode = Bits(width = ACQUIRE_ATOMIC_OP_BITS)
val write_mask = Bits(width = conf.writeMaskBits)
val subword_addr = Bits(width = conf.wordAddrBits)
val atomic_opcode = Bits(width = conf.atomicOpBits)
}
object Probe