initial version, acts like old hub
This commit is contained in:
Henry Cook
parent
d735f64110
commit
dc1a61264d
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@ -96,3 +96,502 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
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io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
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io.write.ready := !rst
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}
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abstract trait L2HellaCacheParameters extends CacheParameters
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with CoherenceAgentParameters
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abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
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abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters
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trait HasL2Id extends Bundle with CoherenceAgentParameters {
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val id = UInt(width = log2Up(nTransactors))
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}
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trait HasL2InternalRequestState extends L2HellaCacheBundle {
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val tag_match = Bool()
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val meta = new L2Metadata
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val way_en = Bits(width = nWays)
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}
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object L2Metadata {
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def apply(tag: Bits, coh: MasterMetadata) = {
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val meta = new L2Metadata
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meta.tag := tag
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meta.coh := coh
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meta
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}
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}
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class L2Metadata extends Metadata with L2HellaCacheParameters {
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val coh = co.masterMetadataOnFlush.clone
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}
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class L2MetaReadReq extends MetaReadReq with HasL2Id {
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val tag = Bits(width = tagBits)
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}
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class L2MetaWriteReq extends MetaWriteReq[L2Metadata](new L2Metadata)
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with HasL2Id
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class L2MetaResp extends L2HellaCacheBundle
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with HasL2Id
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with HasL2InternalRequestState
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class L2MetadataArray extends L2HellaCacheModule {
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val io = new Bundle {
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val read = Decoupled(new L2MetaReadReq).flip
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val write = Decoupled(new L2MetaWriteReq).flip
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val resp = Valid(new L2MetaResp)
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}
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val meta = Module(new MetadataArray(() => L2Metadata(UInt(0), co.masterMetadataOnFlush)))
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meta.io.read <> io.read
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meta.io.write <> io.write
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val s1_clk_en = Reg(next = io.read.fire())
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val s1_tag = RegEnable(io.read.bits.tag, io.read.valid)
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val s1_id = RegEnable(io.read.bits.id, io.read.valid)
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def wayMap[T <: Data](f: Int => T) = Vec((0 until nWays).map(f))
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val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === s1_tag)
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val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && co.isValid(meta.io.resp(w).coh)).toBits
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val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
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val s2_tag_match = s2_tag_match_way.orR
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val s2_hit_coh = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
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//val s2_hit = s2_tag_match && tl.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === tl.co.newStateOnHit(s2_req.cmd, s2_hit_state)
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val replacer = params(Replacer)()
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val s1_replaced_way_en = UIntToOH(replacer.way)
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
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io.resp.valid := Reg(next = s1_clk_en)
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io.resp.bits.id := RegEnable(s1_id, s1_clk_en)
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io.resp.bits.tag_match := s2_tag_match
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io.resp.bits.meta := Mux(s2_tag_match,
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L2Metadata(s2_repl_meta.tag, s2_hit_coh),
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s2_repl_meta)
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io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
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}
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class L2DataReadReq extends L2HellaCacheBundle with HasL2Id {
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val way_en = Bits(width = nWays)
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val addr = Bits(width = params(TLAddrBits))
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}
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class L2DataWriteReq extends L2DataReadReq {
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val wmask = Bits(width = params(TLWriteMaskBits))
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val data = Bits(width = params(TLDataBits))
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}
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class L2DataResp extends Bundle with HasL2Id {
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val data = Bits(width = params(TLDataBits))
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}
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class L2DataArray extends L2HellaCacheModule {
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val io = new Bundle {
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val read = Decoupled(new L2DataReadReq).flip
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val write = Decoupled(new L2DataWriteReq).flip
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val resp = Valid(new L2DataResp)
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}
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val waddr = io.write.bits.addr
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val raddr = io.read.bits.addr
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val wmask = FillInterleaved(wordBits, io.write.bits.wmask)
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val resp = (0 until nWays).map { w =>
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val array = Mem(Bits(width=params(RowBits)), nSets*refillCycles, seqRead = true)
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when (io.write.bits.way_en(w) && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}
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array(RegEnable(raddr, io.read.bits.way_en(w) && io.read.valid))
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}
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io.resp.valid := ShiftRegister(io.read.valid, 2)
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io.resp.bits.id := ShiftRegister(io.read.bits.id, 2)
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io.resp.bits.data := Mux1H(ShiftRegister(io.read.bits.way_en, 2), resp)
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io.read.ready := Bool(true)
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io.write.ready := Bool(true)
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}
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class L2HellaCache(bankId: Int, innerId: String, outerId: String) extends
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CoherenceAgent(innerId, outerId) with L2HellaCacheParameters {
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require(isPow2(nSets))
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require(isPow2(nWays))
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require(refillCycles == 1)
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val tshrfile = Module(new TSHRFile(bankId, innerId, outerId))
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val meta = Module(new L2MetadataArray)
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val data = Module(new L2DataArray)
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tshrfile.io.inner <> io.inner
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tshrfile.io.meta_read <> meta.io.read
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tshrfile.io.meta_write <> meta.io.write
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tshrfile.io.meta_resp <> meta.io.resp
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tshrfile.io.data_read <> data.io.read
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tshrfile.io.data_write <> data.io.write
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tshrfile.io.data_resp <> data.io.resp
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io.outer <> tshrfile.io.outer
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io.incoherent <> tshrfile.io.incoherent
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}
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class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCacheModule {
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val io = new Bundle {
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val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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val incoherent = Vec.fill(nClients){Bool()}.asInput
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val meta_read = Decoupled(new L2MetaReadReq)
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val meta_write = Decoupled(new L2MetaWriteReq)
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val meta_resp = Valid(new L2MetaResp).flip
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val data_read = Decoupled(new L2DataReadReq)
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val data_write = Decoupled(new L2DataWriteReq)
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val data_resp = Valid(new L2DataResp).flip
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}
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// Wiring helper funcs
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def doOutputArbitration[T <: Data](out: DecoupledIO[T], ins: Seq[DecoupledIO[T]]) {
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val arb = Module(new RRArbiter(out.bits.clone, ins.size))
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out <> arb.io.out
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arb.io.in zip ins map { case (a, in) => a <> in }
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}
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def doInputRouting[T <: HasL2Id](in: ValidIO[T], outs: Seq[ValidIO[T]]) {
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outs.map(_.bits := in.bits)
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outs.zipWithIndex.map { case (o, i) => o.valid := UInt(i) === in.bits.id }
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}
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// Create TSHRs for outstanding transactions
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val trackerList = (0 until nReleaseTransactors).map { id =>
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Module(new L2VoluntaryReleaseTracker(id, bankId, innerId, outerId))
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} ++ (nReleaseTransactors until nTransactors).map { id =>
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Module(new L2AcquireTracker(id, bankId, innerId, outerId))
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}
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// Propagate incoherence flags
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trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
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// Handle acquire transaction initiation
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val acquire = io.inner.acquire
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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val block_acquires = any_acquire_conflict
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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t.acquire.valid := alloc_arb.io.in(i).ready
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}
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acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && !block_acquires
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alloc_arb.io.out.ready := acquire.valid && !block_acquires
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// Handle probe requests
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doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe))
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// Handle releases, which might be voluntary and might have data
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val release = io.inner.release
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val voluntary = co.isVoluntary(release.bits.payload)
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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val block_releases = Bool(false)
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
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//val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
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val release_idx = Mux(voluntary, UInt(0), release.bits.payload.master_xact_id)
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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t.release.bits := release.bits
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t.release.valid := release.valid && (release_idx === UInt(i)) && !block_releases
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}
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx) && !block_releases
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// Reply to initial requestor
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doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant))
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// Free finished transactions
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val ack = io.inner.finish
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trackerList.map(_.io.inner.finish.valid := ack.valid)
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trackerList.map(_.io.inner.finish.bits := ack.bits)
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ack.ready := Bool(true)
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// Arbitrate for the outer memory port
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val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size),
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{case TLId => outerId})
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer }
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io.outer <> outer_arb.io.out
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// Local memory
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doOutputArbitration(io.meta_read, trackerList.map(_.io.meta_read))
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doOutputArbitration(io.meta_write, trackerList.map(_.io.meta_write))
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doOutputArbitration(io.data_read, trackerList.map(_.io.data_read))
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doOutputArbitration(io.data_write, trackerList.map(_.io.data_write))
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doInputRouting(io.meta_resp, trackerList.map(_.io.meta_resp))
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doInputRouting(io.data_resp, trackerList.map(_.io.data_resp))
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}
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abstract class L2XactTracker(innerId: String, outerId: String) extends L2HellaCacheModule {
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val io = new Bundle {
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val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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val tile_incoherent = Bits(INPUT, nClients)
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val has_acquire_conflict = Bool(OUTPUT)
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val has_release_conflict = Bool(OUTPUT)
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val meta_read = Decoupled(new L2MetaReadReq)
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val meta_write = Decoupled(new L2MetaWriteReq)
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val meta_resp = Valid(new L2MetaResp).flip
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val data_read = Decoupled(new L2DataReadReq)
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val data_write = Decoupled(new L2DataWriteReq)
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val data_resp = Valid(new L2DataResp).flip
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}
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val c_acq = io.inner.acquire.bits
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val c_rel = io.inner.release.bits
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val c_gnt = io.inner.grant.bits
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val c_ack = io.inner.finish.bits
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val m_gnt = io.outer.grant.bits
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}
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class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
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val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_idle)
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val xact = Reg{ new Release }
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val xact_internal = Reg{ new L2MetaResp }
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val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
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io.has_acquire_conflict := Bool(false)
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) &&
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(state != s_idle)
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io.outer.grant.ready := Bool(false)
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io.outer.acquire.valid := Bool(false)
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io.outer.acquire.bits.header.src := UInt(bankId)
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io.outer.acquire.bits.payload := Bundle(Acquire(co.getUncachedWriteAcquireType,
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xact.addr,
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UInt(trackerId),
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xact.data),
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{ case TLId => outerId })
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io.inner.acquire.ready := Bool(false)
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io.inner.probe.valid := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.grant.valid := Bool(false)
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io.inner.grant.bits.header.src := UInt(bankId)
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io.inner.grant.bits.header.dst := init_client_id
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io.inner.grant.bits.payload := Grant(co.getGrantType(xact, co.masterMetadataOnFlush),// TODO xact_internal.meta)
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xact.client_xact_id,
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UInt(trackerId))
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io.data_read.valid := Bool(false)
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io.data_write.valid := Bool(false)
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io.data_write.bits.id := UInt(trackerId)
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io.data_write.bits.way_en := xact_internal.way_en
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io.data_write.bits.addr := xact.addr
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io.data_write.bits.wmask := SInt(-1)
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io.data_write.bits.data := xact.data
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io.meta_read.valid := Bool(false)
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io.meta_read.bits.id := UInt(trackerId)
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io.meta_read.bits.idx := xact.addr(untagBits-1,blockOffBits)
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io.meta_read.bits.tag := xact.addr >> UInt(untagBits)
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io.meta_write.valid := Bool(false)
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io.meta_write.bits.id := UInt(trackerId)
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io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits)
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io.meta_write.bits.way_en := xact_internal.way_en
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io.meta_write.bits.data := xact_internal.meta
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when(io.meta_resp.valid) { xact_internal := io.meta_resp.bits }
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switch (state) {
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is(s_idle) {
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io.inner.release.ready := Bool(true)
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when( io.inner.release.valid ) {
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xact := c_rel.payload
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init_client_id := c_rel.header.src
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state := s_mem
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}
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}/*
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is(s_meta_read) {
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when(io.meta_read.ready) state := s_meta_resp
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}
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is(s_meta_resp) {
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when(io.meta_resp.valid) {
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xact_internal.meta := tl.co.masterMetadataOnRelease(xact, xact_internal.meta, init_client_id))
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state := Mux(s_meta_write
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Mux(co.messageHasData(xact), s_mem, s_ack)
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}*/
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is(s_mem) {
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io.outer.acquire.valid := Bool(true)
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when(io.outer.acquire.ready) { state := s_ack }
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}
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is(s_ack) {
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io.inner.grant.valid := Bool(true)
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when(io.inner.grant.ready) { state := s_idle }
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}
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}
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}
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class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
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val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_busy :: Nil = Enum(UInt(), 6)
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val state = Reg(init=s_idle)
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val xact = Reg{ new Acquire }
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val xact_internal = Reg{ new L2MetaResp }
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val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
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//TODO: Will need id reg for merged release xacts
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val release_count = if (nClients == 1) UInt(0) else Reg(init=UInt(0, width = log2Up(nClients)))
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val probe_flags = Reg(init=Bits(0, width = nClients))
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val curr_p_id = PriorityEncoder(probe_flags)
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val pending_outer_write = co.messageHasData(xact)
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val pending_outer_read = co.requiresOuterRead(xact.a_type)
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val outer_write_acq = Bundle(Acquire(co.getUncachedWriteAcquireType,
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xact.addr, UInt(trackerId), xact.data),
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{ case TLId => outerId })
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val outer_write_rel = Bundle(Acquire(co.getUncachedWriteAcquireType,
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xact.addr, UInt(trackerId), c_rel.payload.data),
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{ case TLId => outerId })
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val outer_read = Bundle(Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId)),
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{ case TLId => outerId })
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val probe_initial_flags = Bits(width = nClients)
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probe_initial_flags := Bits(0)
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if (nClients > 1) {
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// issue self-probes for uncached read xacts to facilitate I$ coherence
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val probe_self = Bool(true) //co.needsSelfProbe(io.inner.acquire.bits.payload)
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val myflag = Mux(probe_self, Bits(0), UIntToOH(c_acq.header.src(log2Up(nClients)-1,0)))
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probe_initial_flags := ~(io.tile_incoherent | myflag)
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}
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io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) && (state != s_idle)
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) && (state != s_idle)
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io.outer.acquire.valid := Bool(false)
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io.outer.acquire.bits.header.src := UInt(bankId)
|
||||
io.outer.acquire.bits.payload := outer_read
|
||||
io.outer.grant.ready := io.inner.grant.ready
|
||||
|
||||
io.inner.probe.valid := Bool(false)
|
||||
io.inner.probe.bits.header.src := UInt(bankId)
|
||||
io.inner.probe.bits.header.dst := curr_p_id
|
||||
io.inner.probe.bits.payload := Probe(co.getProbeType(xact, /*xact_internal.meta), TODO*/
|
||||
co.masterMetadataOnFlush),
|
||||
xact.addr,
|
||||
UInt(trackerId))
|
||||
|
||||
val grant_type = co.getGrantType(xact, co.masterMetadataOnFlush)// TODO xact_internal.meta)
|
||||
io.inner.grant.valid := Bool(false)
|
||||
io.inner.grant.bits.header.src := UInt(bankId)
|
||||
io.inner.grant.bits.header.dst := init_client_id
|
||||
io.inner.grant.bits.payload := Grant(grant_type,
|
||||
xact.client_xact_id,
|
||||
UInt(trackerId),
|
||||
m_gnt.payload.data)
|
||||
|
||||
io.inner.acquire.ready := Bool(false)
|
||||
io.inner.release.ready := Bool(false)
|
||||
|
||||
io.data_read.valid := Bool(false)
|
||||
io.data_read.bits.id := UInt(trackerId)
|
||||
io.data_read.bits.way_en := xact_internal.way_en
|
||||
io.data_read.bits.addr := xact.addr
|
||||
io.data_write.valid := Bool(false)
|
||||
io.data_write.bits.id := UInt(trackerId)
|
||||
io.data_write.bits.way_en := xact_internal.way_en
|
||||
io.data_write.bits.addr := xact.addr
|
||||
io.data_write.bits.wmask := SInt(-1)
|
||||
io.data_write.bits.data := xact.data
|
||||
io.meta_read.valid := Bool(false)
|
||||
io.meta_read.bits.id := UInt(trackerId)
|
||||
io.meta_read.bits.idx := xact.addr(untagBits-1,blockOffBits)
|
||||
io.meta_read.bits.tag := xact.addr >> UInt(untagBits)
|
||||
io.meta_write.valid := Bool(false)
|
||||
io.meta_write.bits.id := UInt(trackerId)
|
||||
io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits)
|
||||
io.meta_write.bits.way_en := xact_internal.way_en
|
||||
io.meta_write.bits.data := xact_internal.meta
|
||||
|
||||
when(io.meta_resp.valid && io.meta_resp.bits.id === UInt(trackerId)) { xact_internal := io.meta_resp.bits }
|
||||
|
||||
switch (state) {
|
||||
is(s_idle) {
|
||||
io.inner.acquire.ready := Bool(true)
|
||||
val needs_outer_write = co.messageHasData(c_acq.payload)
|
||||
val needs_outer_read = co.requiresOuterRead(c_acq.payload.a_type)
|
||||
when( io.inner.acquire.valid ) {
|
||||
xact := c_acq.payload
|
||||
init_client_id := c_acq.header.src
|
||||
probe_flags := probe_initial_flags
|
||||
if(nClients > 1) {
|
||||
release_count := PopCount(probe_initial_flags)
|
||||
state := Mux(probe_initial_flags.orR, s_probe,
|
||||
Mux(needs_outer_write, s_mem_write,
|
||||
Mux(needs_outer_read, s_mem_read, s_make_grant)))
|
||||
} else state := Mux(needs_outer_write, s_mem_write,
|
||||
Mux(needs_outer_read, s_mem_read, s_make_grant))
|
||||
}
|
||||
}
|
||||
// s_read_meta
|
||||
// xact_internal := resp
|
||||
is(s_probe) {
|
||||
// Generate probes
|
||||
io.inner.probe.valid := probe_flags.orR
|
||||
when(io.inner.probe.ready) {
|
||||
probe_flags := probe_flags & ~(UIntToOH(curr_p_id))
|
||||
}
|
||||
|
||||
// Handle releases, which may have data to be written back
|
||||
when(io.inner.release.valid) {
|
||||
//xact_internal.meta.coh := tl.co.masterMetadataOnRelease(
|
||||
// io.inner.release.bits.payload,
|
||||
// xact_internal.meta.coh,
|
||||
// init_client_id)
|
||||
when(co.messageHasData(c_rel.payload)) {
|
||||
io.outer.acquire.valid := Bool(true)
|
||||
io.outer.acquire.bits.payload := outer_write_rel
|
||||
when(io.outer.acquire.ready) {
|
||||
io.inner.release.ready := Bool(true)
|
||||
if(nClients > 1) release_count := release_count - UInt(1)
|
||||
when(release_count === UInt(1)) {
|
||||
state := Mux(pending_outer_write, s_mem_write,
|
||||
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||||
}
|
||||
}
|
||||
} .otherwise {
|
||||
io.inner.release.ready := Bool(true)
|
||||
if(nClients > 1) release_count := release_count - UInt(1)
|
||||
when(release_count === UInt(1)) {
|
||||
state := Mux(pending_outer_write, s_mem_write,
|
||||
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
is(s_mem_read) {
|
||||
io.outer.acquire.valid := Bool(true)
|
||||
io.outer.acquire.bits.payload := outer_read
|
||||
when(io.outer.acquire.ready) {
|
||||
state := Mux(co.requiresAckForGrant(grant_type), s_busy, s_idle)
|
||||
}
|
||||
}
|
||||
is(s_mem_write) {
|
||||
io.outer.acquire.valid := Bool(true)
|
||||
io.outer.acquire.bits.payload := outer_write_acq
|
||||
when(io.outer.acquire.ready) {
|
||||
state := Mux(pending_outer_read, s_mem_read, s_make_grant)
|
||||
}
|
||||
}
|
||||
is(s_make_grant) {
|
||||
io.inner.grant.valid := Bool(true)
|
||||
when(io.inner.grant.ready) {
|
||||
state := Mux(co.requiresAckForGrant(grant_type), s_busy, s_idle)
|
||||
}
|
||||
}
|
||||
is(s_busy) { // Nothing left to do but wait for transaction to complete
|
||||
when(io.outer.grant.valid && m_gnt.payload.client_xact_id === UInt(trackerId)) {
|
||||
io.inner.grant.valid := Bool(true)
|
||||
}
|
||||
when(io.inner.finish.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
|
||||
state := s_idle
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user