riscv/rocket-chip
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L2 subblock access bugfix

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Yunsup Lee
2015-03-11 01:56:47 -07:00
parent 17072a0041
commit 3ab1aca7de
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/cache.scala
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@@ -412,7 +412,7 @@ class L2XactTrackerIO extends HierarchicalXactTrackerIO {
abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
def connectDataBeatCounter[S <: L2HellaCacheBundle](inc: Bool, data: S, beat: UInt, full_block: Bool) = {
if(data.refillCycles > 1) {
val (multi_cnt, multi_done) = Counter(inc, data.refillCycles)
val (multi_cnt, multi_done) = Counter(full_block && inc, data.refillCycles)
(Mux(!full_block, beat, multi_cnt), Mux(!full_block, inc, multi_done))
} else { (UInt(0), inc) }
}