riscv/rocket-chip
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Merge branch 'master' into chisel-v2

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Conflicts:
	src/main/scala/memserdes.scala
This commit is contained in:
Stephen Twigg
2013-09-05 16:17:34 -07:00
parent 9aff60f340 b01fe4f6aa
commit e23e8e3850
1 changed files with 1 additions and 2 deletions
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3
uncore/src/main/scala/memserdes.scala
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@@ -112,8 +112,7 @@ class MemSerdes(w: Int) extends Module
}
io.wide.resp.valid := resp_val
io.wide.resp.bits.tag := in_buf(io.wide.resp.bits.tag.width-1,0)
io.wide.resp.bits.data := in_buf >> UInt(io.wide.resp.bits.tag.width)
io.wide.resp.bits := io.wide.resp.bits.fromBits(in_buf)
}
class MemDesserIO(w: Int) extends Bundle {