Merge branch 'master' into chisel-v2
Conflicts: src/main/scala/memserdes.scala
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commit
e23e8e3850
@ -112,8 +112,7 @@ class MemSerdes(w: Int) extends Module
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}
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io.wide.resp.valid := resp_val
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io.wide.resp.bits.tag := in_buf(io.wide.resp.bits.tag.width-1,0)
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io.wide.resp.bits.data := in_buf >> UInt(io.wide.resp.bits.tag.width)
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io.wide.resp.bits := io.wide.resp.bits.fromBits(in_buf)
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}
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class MemDesserIO(w: Int) extends Bundle {
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