Revert "make sure L2MetadataArray assigns unoccupied way if available"
This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
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3c95afebc6
commit
04383a31f5
@ -208,14 +208,10 @@ class L2MetadataArray(implicit p: Parameters) extends L2HellaCacheModule()(p) {
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val s1_id = RegEnable(io.read.bits.id, io.read.valid)
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def wayMap[T <: Data](f: Int => T) = Vec((0 until nWays).map(f))
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val s1_clk_en = Reg(next = io.read.fire())
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val s1_free_way = wayMap((w: Int) => !meta.io.resp(w).coh.outer.isValid())
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val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === s1_tag)
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val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && meta.io.resp(w).coh.outer.isValid()).toBits
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val s2_free_way = RegEnable(s1_free_way, s1_clk_en)
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val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
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val s2_tag_match = s2_tag_match_way.orR
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val s2_free = s2_free_way.toBits.orR
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val s2_free_way_en = PriorityEncoderOH(s2_free_way).toBits
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val s2_hit_coh = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
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val replacer = p(Replacer)()
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@ -223,7 +219,7 @@ class L2MetadataArray(implicit p: Parameters) extends L2HellaCacheModule()(p) {
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
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when(!s2_tag_match && !s2_free) { replacer.miss }
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when(!s2_tag_match) { replacer.miss }
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io.resp.valid := Reg(next = s1_clk_en)
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io.resp.bits.id := RegEnable(s1_id, s1_clk_en)
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@ -231,9 +227,7 @@ class L2MetadataArray(implicit p: Parameters) extends L2HellaCacheModule()(p) {
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io.resp.bits.meta := Mux(s2_tag_match,
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L2Metadata(s2_repl_meta.tag, s2_hit_coh),
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s2_repl_meta)
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io.resp.bits.way_en := MuxCase(s2_replaced_way_en, Seq(
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s2_tag_match -> s2_tag_match_way,
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s2_free -> s2_free_way_en))
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io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
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}
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class L2DataReadReq(implicit p: Parameters) extends L2HellaCacheBundle()(p)
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