Voluntary Writeback tracker rewrite
This commit is contained in:
Henry Cook
parent
11b5222d01
commit
09e30041ed
@ -337,8 +337,7 @@ class L2DataArray(delay: Int) extends L2HellaCacheModule {
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io.write.ready := Bool(true)
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}
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class L2HellaCacheBank extends HierarchicalCoherenceAgent
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with L2HellaCacheParameters {
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class L2HellaCacheBank extends HierarchicalCoherenceAgent with L2HellaCacheParameters {
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require(isPow2(nSets))
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require(isPow2(nWays))
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@ -357,8 +356,7 @@ class TSHRFileIO extends HierarchicalTLIO {
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val data = new L2DataRWIO
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}
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class TSHRFile extends L2HellaCacheModule
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with HasCoherenceAgentWiringHelpers {
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class TSHRFile extends L2HellaCacheModule with HasCoherenceAgentWiringHelpers {
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val io = new TSHRFileIO
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// Create TSHRs for outstanding transactions
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@ -381,7 +379,6 @@ class TSHRFile extends L2HellaCacheModule
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val acquire_idx = Mux(acquireMatches.orR,
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PriorityEncoder(acquireMatches),
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PriorityEncoder(acquireReadys))
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val block_acquires = acquireConflicts.orR
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io.inner.acquire.ready := acquireReadys.orR && !block_acquires
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trackerAcquireIOs.zipWithIndex.foreach {
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@ -432,7 +429,7 @@ class L2XactTrackerIO extends HierarchicalXactTrackerIO {
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}
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abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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class CacheBlockBuffer {
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class CacheBlockBuffer { // TODO
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val buffer = Reg(Bits(width = params(CacheBlockBytes)*8))
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def internal = Vec.fill(internalDataBeats){ Bits(width = rowBits) }.fromBits(buffer)
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@ -477,127 +474,118 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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val isPartial = a.wmask() != Acquire.fullWriteMask
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addPendingBitWhenBeat(in.fire() && isPartial && Bool(ignoresWriteMask), a)
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}
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def pinAllReadyValidLow[T <: Data](b: Bundle) {
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b.elements.foreach {
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_._2 match {
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case d: DecoupledIO[T] =>
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if(d.ready.dir == OUTPUT) d.ready := Bool(false)
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else if(d.valid.dir == OUTPUT) d.valid := Bool(false)
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case v: ValidIO[T] => if(v.valid.dir == OUTPUT) v.valid := Bool(false)
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case b: Bundle => pinAllReadyValidLow(b)
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case _ =>
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}
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}
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}
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}
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class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
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val io = new L2XactTrackerIO
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pinAllReadyValidLow(io)
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val s_idle :: s_meta_read :: s_meta_resp :: s_data_write :: s_meta_write :: s_inner_grant :: s_inner_finish :: Nil = Enum(UInt(), 7)
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val s_idle :: s_meta_read :: s_meta_resp :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 5)
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val state = Reg(init=s_idle)
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val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
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val xact_tag_match = Reg{ Bool() }
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val xact_old_meta = Reg{ new L2Metadata }
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val data_buffer = Vec.fill(innerDataBeats){ Reg(init=UInt(0, width = innerDataBits)) }
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val xact_way_en = Reg{ Bits(width = nWays) }
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val data_buffer = Vec.fill(innerDataBeats){ Reg(io.irel().data.clone) }
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val xact_old_meta = Reg{ new L2Metadata }
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val coh = xact_old_meta.coh
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val collect_irel_data = Reg(init=Bool(false))
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val irel_data_valid = Reg(init=Bits(0, width = innerDataBeats))
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val irel_data_done = connectIncomingDataBeatCounter(io.inner.release)
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val (write_data_cnt, write_data_done) = connectInternalDataBeatCounter(io.data.write)
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val pending_irels = Reg(init=Bits(0, width = io.inner.tlDataBeats))
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val pending_writes = Reg(init=Bits(0, width = io.inner.tlDataBeats))
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val pending_ignt = Reg(init=Bool(false))
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io.has_acquire_conflict := Bool(false)
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io.has_acquire_match := Bool(false)
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io.has_release_match := io.irel().isVoluntary()
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val all_pending_done =
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!(pending_writes.orR ||
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pending_ignt)
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io.outer.acquire.valid := Bool(false)
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io.outer.probe.ready := Bool(false)
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io.outer.release.valid := Bool(false)
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io.outer.grant.ready := Bool(false)
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io.inner.acquire.ready := Bool(false)
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io.inner.probe.valid := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.grant.valid := Bool(false)
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io.inner.finish.ready := Bool(false)
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// Accept a voluntary Release (and any further beats of data)
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pending_irels := (pending_irels & dropPendingBitWhenBeatHasData(io.inner.release))
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io.inner.release.ready := state === s_idle || pending_irels.orR
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when(io.inner.release.fire()) { data_buffer(io.irel().addr_beat) := io.irel().data }
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io.inner.grant.bits := coh.inner.makeGrant(xact, UInt(trackerId))
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io.data.read.valid := Bool(false)
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io.data.write.valid := Bool(false)
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io.data.write.bits.id := UInt(trackerId)
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io.data.write.bits.way_en := xact_way_en
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io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB)
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io.data.write.bits.addr_beat := write_data_cnt
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io.data.write.bits.wmask := SInt(-1)
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io.data.write.bits.data := data_buffer(write_data_cnt)
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io.meta.read.valid := Bool(false)
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// Begin a transaction by getting the current block metadata
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io.meta.read.valid := state === s_meta_read
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io.meta.read.bits.id := UInt(trackerId)
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io.meta.read.bits.idx := xact.addr_block(idxMSB,idxLSB)
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io.meta.read.bits.tag := xact.addr_block >> UInt(idxBits)
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io.meta.write.valid := Bool(false)
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// Write the voluntarily written back data to this cache
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pending_writes := (pending_writes & dropPendingBit(io.data.write)) |
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addPendingBitWhenBeatHasData(io.inner.release)
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val curr_write_beat = PriorityEncoder(pending_writes)
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io.data.write.valid := state === s_busy && pending_writes.orR
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io.data.write.bits.id := UInt(trackerId)
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io.data.write.bits.way_en := xact_way_en
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io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB)
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io.data.write.bits.addr_beat := curr_write_beat
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io.data.write.bits.wmask := SInt(-1)
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io.data.write.bits.data := data_buffer(curr_write_beat)
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// Send an acknowledgement
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io.inner.grant.valid := state === s_busy && pending_ignt && !pending_irels
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io.inner.grant.bits := coh.inner.makeGrant(xact, UInt(trackerId))
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when(io.inner.grant.fire()) { pending_ignt := Bool(false) }
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// End a transaction by updating the block metadata
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io.meta.write.valid := state === s_meta_write
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io.meta.write.bits.id := UInt(trackerId)
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io.meta.write.bits.idx := xact.addr_block(idxMSB,idxLSB)
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io.meta.write.bits.way_en := xact_way_en
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io.meta.write.bits.data.tag := xact.addr_block >> UInt(idxBits)
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io.meta.write.bits.data.coh.inner := xact_old_meta.coh.inner.onRelease(xact)
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io.meta.write.bits.data.coh.outer := xact_old_meta.coh.outer.onHit(M_XWR) // WB is a write
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io.wb.req.valid := Bool(false)
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io.meta.write.bits.data.coh.outer := Mux(xact.hasData(),
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xact_old_meta.coh.outer.onHit(M_XWR),
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xact_old_meta.coh.outer)
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when(collect_irel_data) {
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io.inner.release.ready := Bool(true)
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when(io.inner.release.valid) {
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data_buffer(io.irel().addr_beat) := io.irel().data
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irel_data_valid(io.irel().addr_beat) := Bool(true)
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// State machine updates and transaction handler metadata intialization
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when(state === s_idle && io.inner.release.valid) {
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xact := io.irel()
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when(io.irel().hasMultibeatData()) {
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pending_irels := dropPendingBitWhenBeatHasData(io.inner.release)
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}. otherwise {
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pending_irels := UInt(0)
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}
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when(irel_data_done) { collect_irel_data := Bool(false) }
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pending_writes := addPendingBitWhenBeatHasData(io.inner.release)
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pending_ignt := io.irel().requiresAck()
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state := s_meta_read
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}
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when(state === s_meta_read && io.meta.read.ready) { state := s_meta_resp }
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when(state === s_meta_resp && io.meta.resp.valid) {
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xact_old_meta := io.meta.resp.bits.meta
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xact_way_en := io.meta.resp.bits.way_en
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state := s_busy
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}
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when(state === s_busy && all_pending_done) { state := s_meta_write }
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when(state === s_meta_write && io.meta.write.ready) { state := s_idle }
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switch (state) {
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is(s_idle) {
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io.inner.release.ready := Bool(true)
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when( io.inner.release.valid ) {
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xact := io.irel()
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data_buffer(io.irel().addr_beat) := io.irel().data
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collect_irel_data := io.irel().hasMultibeatData()
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irel_data_valid := io.irel().hasData() << io.irel().addr_beat
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state := s_meta_read
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}
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}
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is(s_meta_read) {
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io.meta.read.valid := Bool(true)
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when(io.meta.read.ready) { state := s_meta_resp }
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}
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is(s_meta_resp) {
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when(io.meta.resp.valid) {
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xact_tag_match := io.meta.resp.bits.tag_match
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xact_old_meta := io.meta.resp.bits.meta
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xact_way_en := io.meta.resp.bits.way_en
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state := Mux(io.meta.resp.bits.tag_match,
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Mux(xact.hasData(), s_data_write, s_meta_write),
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Mux(xact.requiresAck(), s_inner_grant, s_idle))
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}
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}
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is(s_data_write) {
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io.data.write.valid := !collect_irel_data || irel_data_valid(write_data_cnt)
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when(write_data_done) { state := s_meta_write }
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}
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is(s_meta_write) {
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io.meta.write.valid := Bool(true)
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when(io.meta.write.ready) {
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state := Mux(xact.requiresAck(), s_inner_grant, s_idle) // Need a Grant.voluntaryAck?
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}
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}
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is(s_inner_grant) {
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io.inner.grant.valid := !collect_irel_data
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when(io.inner.grant.ready) {
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state := Mux(io.ignt().requiresAck(), s_inner_finish, s_idle)
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}
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}
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is(s_inner_finish) {
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io.inner.finish.ready := Bool(true)
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when(io.inner.finish.valid) { state := s_idle }
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}
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}
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// These IOs are used for routing in the parent
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io.has_release_match := io.irel().isVoluntary()
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io.has_acquire_match := Bool(false)
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io.has_acquire_conflict := Bool(false)
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// Checks for illegal behavior
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assert(!(state === s_meta_resp && io.meta.resp.valid && !io.meta.resp.bits.tag_match),
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"VoluntaryReleaseTracker accepted Release for a block not resident in this cache!")
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assert(!(state === s_idle && io.inner.release.fire() && !io.irel().isVoluntary()),
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"VoluntaryReleaseTracker accepted Release that wasn't voluntary!")
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}
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class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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val io = new L2XactTrackerIO
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pinAllReadyValidLow(io)
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val s_idle :: s_meta_read :: s_meta_resp :: s_wb_req :: s_wb_resp :: s_inner_probe :: s_outer_acquire :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 9)
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val state = Reg(init=s_idle)
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@ -742,6 +730,20 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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// Track whether any beats are missing from a PutBlock
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pending_puts := (pending_puts & dropPendingBitWhenBeatHasData(io.inner.acquire))
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// Begin a transaction by getting the current block metadata
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io.meta.read.valid := state === s_meta_read
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io.meta.read.bits.id := UInt(trackerId)
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io.meta.read.bits.idx := xact.addr_block(idxMSB,idxLSB)
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io.meta.read.bits.tag := xact.addr_block >> UInt(idxBits)
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// Issue a request to the writeback unit
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io.wb.req.valid := state === s_wb_req
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io.wb.req.bits.id := UInt(trackerId)
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io.wb.req.bits.idx := xact.addr_block(idxMSB,idxLSB)
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io.wb.req.bits.tag := xact_old_meta.tag
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io.wb.req.bits.coh := xact_old_meta.coh
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io.wb.req.bits.way_en := xact_way_en
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// Track which clients yet need to be probed and make Probe message
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pending_iprbs := pending_iprbs & dropPendingBitAtDest(io.inner.probe)
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val curr_probe_dst = PriorityEncoder(pending_iprbs)
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@ -773,10 +775,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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op_code = xact.op_code()),
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Bundle(Acquire(xact))(outerTLParams))
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// Probes from the outer memory system are handled in the WritebackUnit
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io.outer.probe.ready := Bool(false)
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io.outer.release.valid := Bool(false)
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// Handle the response from outer memory
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io.outer.grant.ready := state === s_busy
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val pending_coh_on_ognt = HierarchicalMetadata(
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ManagerMetadata.onReset,
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@ -853,11 +852,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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io.data.write.bits.wmask := wmask_buffer(curr_write_beat)
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io.data.write.bits.data := data_buffer(curr_write_beat)
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io.meta.read.valid := state === s_meta_read
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io.meta.read.bits.id := UInt(trackerId)
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io.meta.read.bits.idx := xact.addr_block(idxMSB,idxLSB)
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io.meta.read.bits.tag := xact.addr_block >> UInt(idxBits)
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// End a transaction by updating the block metadata
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io.meta.write.valid := state === s_meta_write
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io.meta.write.bits.id := UInt(trackerId)
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io.meta.write.bits.idx := xact.addr_block(idxMSB,idxLSB)
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@ -865,13 +860,6 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
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io.meta.write.bits.data.tag := xact.addr_block >> UInt(idxBits)
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io.meta.write.bits.data.coh := pending_coh
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io.wb.req.valid := state === s_wb_req
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io.wb.req.bits.id := UInt(trackerId)
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io.wb.req.bits.idx := xact.addr_block(idxMSB,idxLSB)
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io.wb.req.bits.tag := xact_old_meta.tag
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io.wb.req.bits.coh := xact_old_meta.coh
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io.wb.req.bits.way_en := xact_way_en
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// Handling of secondary misses (Gets and Puts only for now)
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when(io.inner.acquire.fire() && io.iacq().hasData()) { // state <= s_meta_wrtie
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val beat = io.iacq().addr_beat
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@ -988,6 +976,7 @@ class L2WritebackUnitIO extends HierarchicalXactTrackerIO {
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class L2WritebackUnit(trackerId: Int) extends L2XactTracker {
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val io = new L2WritebackUnitIO
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pinAllReadyValidLow(io)
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val s_idle :: s_inner_probe :: s_busy :: s_outer_grant :: s_wb_resp :: Nil = Enum(UInt(), 5)
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val state = Reg(init=s_idle)
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@ -1086,11 +1075,4 @@ class L2WritebackUnit(trackerId: Int) extends L2XactTracker {
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io.has_release_match := io.irel().conflicts(xact_addr_block) && !io.irel().isVoluntary() && io.inner.release.ready
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io.has_acquire_match := Bool(false)
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io.has_acquire_conflict := Bool(false)
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// IOs pinned low
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io.outer.acquire.valid := Bool(false)
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io.outer.probe.ready := Bool(false) // TODO: handle these here
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io.inner.grant.valid := Bool(false)
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io.inner.acquire.ready := Bool(false)
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io.inner.finish.ready := Bool(false)
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}
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