L2-specific metadataarray wrapper, hookups to tshrfile
This commit is contained in:
Henry Cook
parent
bc3ef1011e
commit
0e39346a12
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@ -43,6 +43,7 @@ case class L2CacheConfig(
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def rowoffbits = log2Up(rowbytes)
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def refillcycles = tl.dataBits/(rowbits)
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def statebits = log2Up(states)
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def nTSHRs = nReleaseTransactions + nAcquireTransactions
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require(states > 0)
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require(isPow2(sets))
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@ -60,6 +61,16 @@ abstract trait L2CacheBundle extends Bundle {
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override def clone = this.getClass.getConstructors.head.newInstance(l2cacheconf).asInstanceOf[this.type]
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}
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trait HasL2Id extends L2CacheBundle {
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val id = UInt(width = log2Up(l2cacheconf.nTSHRs))
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}
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trait HasL2InternalRequestState extends L2CacheBundle {
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val tag_match = Bool()
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val old_meta = new L2MetaData
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val way_en = Bits(width = l2cacheconf.ways)
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}
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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@ -80,20 +91,6 @@ abstract class MetaData(implicit val cacheconf: CacheConfig) extends CacheBundle
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val tag = Bits(width = cacheconf.tagbits)
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}
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class L2MetaData(implicit val l2cacheconf: L2CacheConfig) extends MetaData
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with L2CacheBundle {
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val state = UInt(width = l2cacheconf.statebits)
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val sharers = Bits(width = l2cacheconf.tl.ln.nClients)
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}
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/*
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class L3MetaData(implicit conf: L3CacheConfig) extends MetaData()(conf) {
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val cstate = UInt(width = cacheconf.cstatebits)
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val mstate = UInt(width = cacheconf.mstatebits)
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val sharers = Bits(width = cacheconf.tl.ln.nClients)
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}
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*/
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class MetaReadReq(implicit val cacheconf: CacheConfig) extends CacheBundle {
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val idx = Bits(width = cacheconf.idxbits)
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}
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@ -137,49 +134,125 @@ class MetaDataArray[T <: MetaData](gen: () => T)(implicit conf: CacheConfig) ext
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io.write.ready := !rst
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}
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class L2DataReadReq(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle {
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object L2MetaData {
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def apply(tag: Bits, state: UInt, sharers: UInt)(implicit conf: L2CacheConfig) = {
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val meta = new L2MetaData
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meta.tag := tag
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meta.state := state
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meta.sharers := sharers
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meta
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}
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}
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class L2MetaData(implicit val l2cacheconf: L2CacheConfig) extends MetaData
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with L2CacheBundle {
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val state = UInt(width = l2cacheconf.statebits)
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val sharers = Bits(width = l2cacheconf.tl.ln.nClients)
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}
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/*
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class L3MetaData(implicit conf: L3CacheConfig) extends MetaData()(conf) {
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val cstate = UInt(width = cacheconf.cstatebits)
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val mstate = UInt(width = cacheconf.mstatebits)
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val sharers = Bits(width = cacheconf.tl.ln.nClients)
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}
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*/
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class L2MetaReadReq(implicit val l2cacheconf: L2CacheConfig) extends MetaReadReq
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with HasL2Id {
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val tag = Bits(width = l2cacheconf.tagbits)
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}
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class L2MetaWriteReq(implicit val l2cacheconf: L2CacheConfig) extends MetaWriteReq[L2MetaData](new L2MetaData)
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with HasL2Id
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class L2MetaResp(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle
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with HasL2Id
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with HasL2InternalRequestState
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class L2MetaDataArray(implicit conf: L2CacheConfig) extends Module {
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implicit val tl = conf.tl
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val io = new Bundle {
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val read = Decoupled(new L2MetaReadReq).flip
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val write = Decoupled(new L2MetaWriteReq).flip
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val resp = Valid(new L2MetaResp)
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}
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val meta = Module(new MetaDataArray(() => L2MetaData(UInt(0), tl.co.newStateOnFlush, UInt(0))))
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meta.io.read <> io.read
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meta.io.write <> io.write
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val s1_clk_en = Reg(next = io.read.fire())
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val s1_tag = RegEnable(io.read.bits.tag, io.read.valid)
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val s1_id = RegEnable(io.read.bits.id, io.read.valid)
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def wayMap[T <: Data](f: Int => T) = Vec((0 until conf.ways).map(f))
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val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === s1_tag)
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val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && tl.co.isValid(meta.io.resp(w).state)).toBits
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val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
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val s2_tag_match = s2_tag_match_way.orR
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val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).state, s1_clk_en)))
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val s2_hit_sharers = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).sharers, s1_clk_en)))
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val replacer = new RandomReplacement
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val s1_replaced_way_en = UIntToOH(replacer.way)
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
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io.resp.valid := Reg(next = s1_clk_en)
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io.resp.bits.id := RegEnable(s1_id, s1_clk_en)
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io.resp.bits.tag_match := s2_tag_match
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io.resp.bits.old_meta := Mux(s2_tag_match,
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L2MetaData(s2_repl_meta.tag, s2_hit_state, s2_hit_sharers),
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s2_repl_meta)
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io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
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}
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class L2DataReadReq(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle
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with HasL2Id {
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val way_en = Bits(width = l2cacheconf.ways)
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val addr = Bits(width = l2cacheconf.tl.addrBits)
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}
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class L2DataWriteReq(implicit conf: L2CacheConfig) extends L2DataReadReq()(conf) {
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val wmask = Bits(width = conf.tl.writeMaskBits)
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val data = Bits(width = conf.tl.dataBits)
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class L2DataWriteReq(implicit l2cacheconf: L2CacheConfig) extends L2DataReadReq {
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val wmask = Bits(width = l2cacheconf.tl.writeMaskBits)
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val data = Bits(width = l2cacheconf.tl.dataBits)
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}
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class L2DataResp(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle
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with HasL2Id {
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val data = Bits(width = l2cacheconf.tl.dataBits)
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}
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class L2DataArray(implicit conf: L2CacheConfig) extends Module {
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val io = new Bundle {
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val read = Decoupled(new L2DataReadReq).flip
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val write = Decoupled(new L2DataWriteReq).flip
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val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.tl.dataBits)}
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val resp = Valid(new L2DataResp)
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}
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val waddr = io.write.bits.addr
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val raddr = io.read.bits.addr
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val wmask = FillInterleaved(conf.wordbits, io.write.bits.wmask)
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for (w <- 0 until conf.ways) {
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val resp = (0 until conf.ways).map { w =>
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val array = Mem(Bits(width=conf.rowbits), conf.sets*conf.refillcycles, seqRead = true)
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when (io.write.bits.way_en(w) && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}
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io.resp(w) := array(RegEnable(raddr, io.read.bits.way_en(w) && io.read.valid))
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array(RegEnable(raddr, io.read.bits.way_en(w) && io.read.valid))
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}
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io.resp.valid := ShiftRegister(io.read.valid, 2)
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io.resp.bits.id := ShiftRegister(io.read.bits.id, 2)
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io.resp.bits.data := Mux1H(ShiftRegister(io.read.bits.way_en, 2), resp)
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io.read.ready := Bool(true)
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io.write.ready := Bool(true)
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}
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trait L2InternalRequestState extends L2CacheBundle {
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val tag_match = Bool()
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val old_meta = new L2MetaData
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val way_en = Bits(width = l2cacheconf.ways)
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}
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class L2InternalAcquire(implicit val l2cacheconf: L2CacheConfig) extends Acquire()(l2cacheconf.tl)
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with L2InternalRequestState
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with HasL2InternalRequestState
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class L2InternalRelease(implicit val l2cacheconf: L2CacheConfig) extends Release()(l2cacheconf.tl)
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with L2InternalRequestState
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with HasL2InternalRequestState
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class InternalTileLinkIO(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle {
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implicit val (tl, ln) = (l2cacheconf.tl, l2cacheconf.tl.ln)
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@ -194,23 +267,16 @@ class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceA
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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val tshrfile = Module(new TSHRFile(bankId))
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// tags
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val meta = Module(new MetaDataArray(() => new L2MetaData))
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// data
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val meta = Module(new L2MetaDataArray)
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val data = Module(new L2DataArray)
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// replacement policy
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val replacer = new RandomReplacement
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/*
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val s1_replaced_way_en = UIntToOH(replacer.way)
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
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*/
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tshrfile.io.inner <> io.inner
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tshrfile.io.meta_read <> meta.io.read
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tshrfile.io.meta_write <> meta.io.write
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tshrfile.io.meta_resp <> meta.io.resp
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tshrfile.io.data_read <> data.io.read
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tshrfile.io.data_write <> data.io.write
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tshrfile.io.data_resp <> data.io.resp
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io.outer <> tshrfile.io.outer
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io.incoherent <> tshrfile.io.incoherent
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}
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@ -219,19 +285,31 @@ class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceA
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class TSHRFile(bankId: Int)(implicit conf: L2CacheConfig) extends Module {
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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val io = new Bundle {
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val inner = (new InternalTileLinkIO).flip
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val inner = (new TileLinkIO).flip
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val outer = new UncachedTileLinkIO
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val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
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val meta_read_req = Decoupled(new MetaReadReq)
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val meta_write_req = Decoupled(new MetaWriteReq(new L2MetaData))
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val data_read_req = Decoupled(new L2DataReadReq)
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val data_write_req = Decoupled(new L2DataWriteReq)
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val meta_read = Decoupled(new L2MetaReadReq)
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val meta_write = Decoupled(new L2MetaWriteReq)
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val meta_resp = Valid(new L2MetaResp).flip
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val data_read = Decoupled(new L2DataReadReq)
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val data_write = Decoupled(new L2DataWriteReq)
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val data_resp = Valid(new L2DataResp).flip
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}
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// Wiring helper funcs
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def doOutputArbitration[T <: Data](out: DecoupledIO[T], ins: Seq[DecoupledIO[T]]) {
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val arb = Module(new RRArbiter(out.bits.clone, ins.size))
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out <> arb.io.out
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arb.io.in zip ins map { case (a, i) => a <> i }
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}
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// Create TSHRs for outstanding transactions
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val nTrackers = conf.nReleaseTransactions + conf.nAcquireTransactions
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val trackerList = (0 until conf.nReleaseTransactions).map(id => Module(new L2VoluntaryReleaseTracker(id, bankId))) ++
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(conf.nReleaseTransactions until nTrackers).map(id => Module(new L2AcquireTracker(id, bankId)))
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val trackerList = (0 until conf.nReleaseTransactions).map { id =>
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Module(new L2VoluntaryReleaseTracker(id, bankId))
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} ++ (conf.nReleaseTransactions until nTrackers).map { id =>
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Module(new L2AcquireTracker(id, bankId))
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}
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// Propagate incoherence flags
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trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
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@ -251,10 +329,11 @@ class TSHRFile(bankId: Int)(implicit conf: L2CacheConfig) extends Module {
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acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && !block_acquires
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alloc_arb.io.out.ready := acquire.valid && !block_acquires
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// Handle probe request generation
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val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
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io.inner.probe <> probe_arb.io.out
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probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.probe }
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// Handle probe requests
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doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe))
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//val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
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//io.inner.probe <> probe_arb.io.out
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//probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.probe }
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// Handle releases, which might be voluntary and might have data
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val release = io.inner.release
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@ -272,9 +351,10 @@ class TSHRFile(bankId: Int)(implicit conf: L2CacheConfig) extends Module {
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx) && !block_releases
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// Reply to initial requestor
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val grant_arb = Module(new Arbiter(new LogicalNetworkIO(new Grant), trackerList.size))
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io.inner.grant <> grant_arb.io.out
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grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.grant }
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doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant))
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//val grant_arb = Module(new Arbiter(new LogicalNetworkIO(new Grant), trackerList.size))
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//io.inner.grant <> grant_arb.io.out
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//grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.grant }
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// Free finished transactions
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val ack = io.inner.finish
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@ -282,21 +362,35 @@ class TSHRFile(bankId: Int)(implicit conf: L2CacheConfig) extends Module {
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trackerList.map(_.io.inner.finish.bits := ack.bits)
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ack.ready := Bool(true)
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// Create an arbiter for the one memory port
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// Arbitrate for the outer memory port
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val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size))
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer }
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io.outer <> outer_arb.io.out
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// Local memory
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doOutputArbitration(io.meta_read, trackerList.map(_.io.meta_read))
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doOutputArbitration(io.meta_write, trackerList.map(_.io.meta_write))
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doOutputArbitration(io.data_read, trackerList.map(_.io.data_read))
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doOutputArbitration(io.data_write, trackerList.map(_.io.data_write))
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}
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abstract class L2XactTracker()(implicit conf: L2CacheConfig) extends Module {
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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val io = new Bundle {
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val inner = (new InternalTileLinkIO).flip
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val inner = (new TileLinkIO).flip
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val outer = new UncachedTileLinkIO
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val tile_incoherent = Bits(INPUT, ln.nClients)
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val has_acquire_conflict = Bool(OUTPUT)
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val has_release_conflict = Bool(OUTPUT)
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val meta_read = Decoupled(new L2MetaReadReq)
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val meta_write = Decoupled(new L2MetaWriteReq)
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val meta_resp = Valid(new L2MetaResp).flip
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val data_read = Decoupled(new L2DataReadReq)
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val data_write = Decoupled(new L2DataWriteReq)
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val data_resp = Valid(new L2DataResp).flip
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}
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val c_acq = io.inner.acquire.bits
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