moved ecc lib to uncore, l2 checks for partial write masks when ecc is enabled
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@ -15,6 +15,7 @@ case object NPrimaryMisses extends Field[Int]
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case object NSecondaryMisses extends Field[Int]
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case object CacheBlockBytes extends Field[Int]
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case object CacheBlockOffsetBits extends Field[Int]
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case object ECCCode extends Field[Option[Code]]
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abstract trait CacheParameters extends UsesParameters {
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val nSets = params(NSets)
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@ -28,6 +29,7 @@ abstract trait CacheParameters extends UsesParameters {
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val rowBits = params(RowBits)
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val rowBytes = rowBits/8
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val rowOffBits = log2Up(rowBytes)
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val code = params(ECCCode).getOrElse(new IdentityCode)
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}
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abstract class CacheBundle extends Bundle with CacheParameters
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@ -176,6 +178,7 @@ abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgen
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require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states
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val nSecondaryMisses = params(NSecondaryMisses)
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val isLastLevelCache = true
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val ignoresWriteMask = !params(ECCCode).isEmpty
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}
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abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
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@ -462,6 +465,12 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters {
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def dropPendingBitInternal[T <: HasL2BeatAddr] (in: ValidIO[T]) =
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~Fill(in.bits.refillCycles, in.valid) | ~UIntToOH(in.bits.addr_beat)
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def addPendingBitWhenBeatHasPartialWritemask(in: DecoupledIO[LogicalNetworkIO[Acquire]]): UInt = {
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val a = in.bits.payload
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val isPartial = a.wmask() != Acquire.fullWriteMask
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addPendingBitWhenBeat(in.fire() && isPartial && Bool(ignoresWriteMask), in.bits.payload)
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}
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}
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class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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@ -805,7 +814,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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dropPendingBit(io.data.read) &
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dropPendingBitWhenBeatHasData(io.inner.release) &
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dropPendingBitWhenBeatHasData(io.outer.grant)) |
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addPendingBitWhenBeatIsGetOrAtomic(io.inner.acquire)
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addPendingBitWhenBeatIsGetOrAtomic(io.inner.acquire) |
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addPendingBitWhenBeatHasPartialWritemask(io.inner.acquire)
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val curr_read_beat = PriorityEncoder(pending_reads)
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io.data.read.valid := state === s_busy &&
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pending_reads.orR &&
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@ -880,7 +890,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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pending_reads := Mux(
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io.iacq().isBuiltInType(Acquire.getBlockType) || !io.iacq().isBuiltInType(),
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SInt(-1, width = innerDataBeats),
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addPendingBitWhenBeatIsGetOrAtomic(io.inner.acquire)).toUInt
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(addPendingBitWhenBeatIsGetOrAtomic(io.inner.acquire) |
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addPendingBitWhenBeatHasPartialWritemask(io.inner.acquire)).toUInt)
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pending_writes := addPendingBitWhenBeatHasData(io.inner.acquire)
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pending_resps := UInt(0)
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pending_ignt_data := UInt(0)
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146
uncore/src/main/scala/ecc.scala
Normal file
146
uncore/src/main/scala/ecc.scala
Normal file
@ -0,0 +1,146 @@
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// See LICENSE for license details.
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package uncore
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import Chisel._
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abstract class Decoding
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{
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def uncorrected: Bits
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def corrected: Bits
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def correctable: Bool
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def uncorrectable: Bool
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def error = correctable || uncorrectable
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}
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abstract class Code
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{
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def width(w0: Int): Int
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def encode(x: Bits): Bits
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def decode(x: Bits): Decoding
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}
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class IdentityCode extends Code
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{
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def width(w0: Int) = w0
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def encode(x: Bits) = x
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def decode(y: Bits) = new Decoding {
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def uncorrected = y
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def corrected = y
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def correctable = Bool(false)
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def uncorrectable = Bool(false)
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}
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}
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class ParityCode extends Code
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{
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def width(w0: Int) = w0+1
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def encode(x: Bits) = Cat(x.xorR, x)
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def decode(y: Bits) = new Decoding {
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def uncorrected = y(y.getWidth-2,0)
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def corrected = uncorrected
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def correctable = Bool(false)
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def uncorrectable = y.xorR
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}
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}
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class SECCode extends Code
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{
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def width(k: Int) = {
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val m = new Unsigned(k).log2 + 1
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k + m + (if((1 << m) < m+k+1) 1 else 0)
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}
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def encode(x: Bits) = {
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val k = x.getWidth
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require(k > 0)
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val n = width(k)
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val y = for (i <- 1 to n) yield {
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if (isPow2(i)) {
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val r = for (j <- 1 to n; if j != i && (j & i) != 0)
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yield x(mapping(j))
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r reduce (_^_)
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} else
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x(mapping(i))
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}
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Vec(y).toBits
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}
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def decode(y: Bits) = new Decoding {
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val n = y.getWidth
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require(n > 0 && !isPow2(n))
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val p2 = for (i <- 0 until log2Up(n)) yield 1 << i
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val syndrome = p2 map { i =>
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val r = for (j <- 1 to n; if (j & i) != 0)
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yield y(j-1)
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r reduce (_^_)
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}
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val s = Vec(syndrome).toBits
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private def swizzle(z: Bits) = Vec((1 to n).filter(i => !isPow2(i)).map(i => z(i-1))).toBits
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def uncorrected = swizzle(y)
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def corrected = swizzle(((y.toUInt << UInt(1)) ^ UIntToOH(s)) >> UInt(1))
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def correctable = s.orR
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def uncorrectable = Bool(false)
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}
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private def mapping(i: Int) = i-1-log2Up(i)
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}
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class SECDEDCode extends Code
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{
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private val sec = new SECCode
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private val par = new ParityCode
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def width(k: Int) = sec.width(k)+1
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def encode(x: Bits) = par.encode(sec.encode(x))
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def decode(x: Bits) = new Decoding {
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val secdec = sec.decode(x(x.getWidth-2,0))
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val pardec = par.decode(x)
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def uncorrected = secdec.uncorrected
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def corrected = secdec.corrected
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def correctable = pardec.uncorrectable
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def uncorrectable = !pardec.uncorrectable && secdec.correctable
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}
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}
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object ErrGen
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{
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// generate a 1-bit error with approximate probability 2^-f
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def apply(width: Int, f: Int): Bits = {
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require(width > 0 && f >= 0 && log2Up(width) + f <= 16)
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UIntToOH(LFSR16()(log2Up(width)+f-1,0))(width-1,0)
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}
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def apply(x: Bits, f: Int): Bits = x ^ apply(x.getWidth, f)
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}
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class SECDEDTest extends Module
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{
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val code = new SECDEDCode
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val k = 4
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val n = code.width(k)
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val io = new Bundle {
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val original = Bits(OUTPUT, k)
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val encoded = Bits(OUTPUT, n)
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val injected = Bits(OUTPUT, n)
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val uncorrected = Bits(OUTPUT, k)
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val corrected = Bits(OUTPUT, k)
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val correctable = Bool(OUTPUT)
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val uncorrectable = Bool(OUTPUT)
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}
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val c = Counter(Bool(true), 1 << k)
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val numErrors = Counter(c._2, 3)._1
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val e = code.encode(c._1)
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val i = e ^ Mux(numErrors < UInt(1), UInt(0), ErrGen(n, 1)) ^ Mux(numErrors < UInt(2), UInt(0), ErrGen(n, 1))
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val d = code.decode(i)
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io.original := c._1
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io.encoded := e
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io.injected := i
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io.uncorrected := d.uncorrected
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io.corrected := d.corrected
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io.correctable := d.correctable
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io.uncorrectable := d.uncorrectable
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}
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@ -132,8 +132,10 @@ class HierarchicalXactTrackerIO extends HierarchicalTLIO with HasTrackerConflict
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abstract class XactTracker extends CoherenceAgentModule
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with HasDataBeatCounters {
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def addPendingBitWhenBeat[T <: HasBeat](inc: Bool, in: T): UInt = Fill(in.tlDataBeats, inc) & UIntToOH(in.addr_beat)
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def dropPendingBitWhenBeat[T <: HasBeat](dec: Bool, in: T): UInt = ~Fill(in.tlDataBeats, dec) | ~UIntToOH(in.addr_beat)
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def addPendingBitWhenBeat[T <: HasBeat](inc: Bool, in: T): UInt =
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Fill(in.tlDataBeats, inc) & UIntToOH(in.addr_beat)
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def dropPendingBitWhenBeat[T <: HasBeat](dec: Bool, in: T): UInt =
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~Fill(in.tlDataBeats, dec) | ~UIntToOH(in.addr_beat)
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def addPendingBitWhenBeatHasData[T <: Data : TypeTag](in: DecoupledIO[T]): UInt = {
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in.bits match {
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@ -5,6 +5,14 @@ package uncore
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import Chisel._
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import scala.math._
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class Unsigned(x: Int) {
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require(x >= 0)
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def clog2: Int = { require(x > 0); ceil(log(x)/log(2)).toInt }
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def log2: Int = { require(x > 0); floor(log(x)/log(2)).toInt }
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def isPow2: Boolean = x > 0 && (x & (x-1)) == 0
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def nextPow2: Int = if (x == 0) 1 else 1 << clog2
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}
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object MuxBundle {
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def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
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mapping.reverse.foldLeft(default)((b, a) => Mux(a._1, a._2, b))
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