riscv/rocket-chip
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Use Vec.fill, not Vec.apply, when making Vec literals

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This commit is contained in:
Andrew Waterman
2015-09-25 17:06:24 -07:00
parent 2179cb64ae
commit 20b7a82ab6
2 changed files with 3 additions and 3 deletions
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4
uncore/src/main/scala/rtc.scala
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@@ -17,12 +17,12 @@ class RTC(pcr_MTIME: Int) extends Module with HTIFParameters {
val sending_addr = Reg(init = Bool(false))
val sending_data = Reg(init = Bool(false))
val send_acked = Reg(init = Vec(nCores, Bool(true)))
val send_acked = Reg(init = Vec.fill(nCores)(Bool(true)))
val coreId = Wire(UInt(width = log2Up(nCores)))
when (rtc_tick) {
rtc := rtc + UInt(1)
send_acked := Vec(nCores, Bool(false))
send_acked := Vec.fill(nCores)(Bool(false))
sending_addr := Bool(true)
sending_data := Bool(true)
}

2
uncore/src/main/scala/tilelink.scala
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@@ -1263,7 +1263,7 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
val roq_data = Reg(Vec(dType.cloneType, size))
val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
val roq_free = Reg(init = Vec(size, Bool(true)))
val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
val roq_enq_addr = PriorityEncoder(roq_free)
val roq_deq_addr = PriorityEncoder(roq_tags.map(_ === io.deq.tag))