riscv/rocket-chip
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Fix incompatible assignment

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This commit is contained in:
Andrew Waterman 2015-07-31 00:59:34 -07:00
parent 377e17e811
commit 6d574f8c1b
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/broadcast.scala
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@ -37,7 +37,7 @@ class L2BroadcastHub extends ManagerCoherenceAgent
Module(new BroadcastAcquireTracker(id), {case TLDataBits => internalDataBits}))
// Propagate incoherence flags
trackerList.map(_.io.incoherent := io.incoherent.toBits)
trackerList.map(_.io.incoherent := io.incoherent)
// Queue to store impending Put data
val sdq = Reg(Vec.fill(sdqDepth){io.iacq().data})