riscv/rocket-chip
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make sure correct parameters are used for TileLink constructors

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This commit is contained in:
Howard Mao
2015-10-14 17:58:35 -07:00
parent 7fa3eb95e3
commit 1d362d6d3a
2 changed files with 16 additions and 9 deletions
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12
uncore/src/main/scala/broadcast.scala
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@@ -250,24 +250,26 @@ class BroadcastAcquireTracker(trackerId: Int)
!io.irel().isVoluntary() &&
(state === s_probe)
val outerParams = p.alterPartial({ case TLId => outerTLId })
val oacq_probe = PutBlock(
client_xact_id = UInt(trackerId),
addr_block = io.irel().addr_block,
addr_beat = io.irel().addr_beat,
data = io.irel().data)
data = io.irel().data)(outerParams)
val oacq_write_beat = Put(
client_xact_id = UInt(trackerId),
addr_block = xact.addr_block,
addr_beat = xact.addr_beat,
data = xact.data_buffer(0),
wmask = xact.wmask())
wmask = xact.wmask())(outerParams)
val oacq_write_block = PutBlock(
client_xact_id = UInt(trackerId),
addr_block = xact.addr_block,
addr_beat = oacq_data_cnt,
data = xact.data_buffer(oacq_data_cnt))
data = xact.data_buffer(oacq_data_cnt))(outerParams)
val oacq_read_beat = Get(
client_xact_id = UInt(trackerId),
@@ -275,11 +277,11 @@ class BroadcastAcquireTracker(trackerId: Int)
addr_beat = xact.addr_beat,
addr_byte = xact.addr_byte(),
operand_size = xact.op_size(),
alloc = Bool(false))
alloc = Bool(false))(outerParams)
val oacq_read_block = GetBlock(
client_xact_id = UInt(trackerId),
addr_block = xact.addr_block)
addr_block = xact.addr_block)(outerParams)
io.outer.acquire.valid := Bool(false)
io.outer.acquire.bits := Mux(state === s_probe, oacq_probe,

13
uncore/src/main/scala/tilelink.scala
View File

@@ -1537,9 +1537,11 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)(implicit p: Param
val outerDataBeats = outerParams.dataBeats
val outerDataBits = outerParams.dataBitsPerBeat
val outerWriteMaskBits = outerParams.writeMaskBits
require(outerDataBeats >= innerDataBeats)
require(outerDataBeats % innerDataBeats == 0)
require(outerDataBits >= innerDataBits)
require(outerDataBits <= innerDataBits)
require(outerDataBits * outerDataBeats == innerDataBits * innerDataBeats)
val factor = outerDataBeats / innerDataBeats
@@ -1562,10 +1564,13 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)(implicit p: Param
val acq_addr_beat = Reg(iacq.addr_beat)
val oacq_ctr = Counter(factor)
val outerConfig = p.alterPartial({ case TLId => outerTLId })
val innerConfig = p.alterPartial({ case TLId => innerTLId })
val get_block_acquire = GetBlock(
client_xact_id = iacq.client_xact_id,
addr_block = iacq.addr_block,
alloc = iacq.allocate())
alloc = iacq.allocate())(outerConfig)
val put_block_acquire = PutBlock(
client_xact_id = acq_client_id,
@@ -1574,7 +1579,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)(implicit p: Param
Cat(acq_addr_beat, oacq_ctr.value)
else acq_addr_beat,
data = acq_data_buffer(outerDataBits - 1, 0),
wmask = acq_wmask_buffer(outerWriteMaskBits - 1, 0))
wmask = acq_wmask_buffer(outerWriteMaskBits - 1, 0))(outerConfig)
val sending_put = Reg(init = Bool(false))
@@ -1614,7 +1619,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)(implicit p: Param
client_xact_id = gnt_client_id,
manager_xact_id = gnt_manager_id,
addr_beat = ignt_ctr.value,
data = gnt_data_buffer.toBits)
data = gnt_data_buffer.toBits)(innerConfig)
io.in.grant.valid := sending_get || (io.out.grant.valid && !ognt_block)
io.out.grant.ready := !sending_get && (ognt_block || io.in.grant.ready)