riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 7bc38383de add (non-working) blocking data cache 2016-05-20 18:59:05 -07:00
Andrew Waterman 4aef567a80 Fix MMIO bug: replay_next wasn't set 2016-05-13 17:59:53 -07:00
Andrew Waterman 742c05d6a7 Pipeline D$->I$ control paths 
These stretch the miss latency by a cycle in exchange for slack.
The current implementation also adds a cycle to mul/div latency,
which can be worked around for more hardware (possibly gated by
the FastMulDiv option).
 2016-05-13 17:07:28 -07:00
Andrew Waterman 9dd23a603a Remove HTIF port 2016-05-03 13:41:58 -07:00
Andrew Waterman 5352497edb MPRV takes effect regardless of privilege mode 2016-05-02 19:53:25 -07:00
Andrew Waterman f784f4da93 Rename PRCICoreIO to PRCITileIO 2016-05-02 18:08:01 -07:00
Andrew Waterman 000e20f937 Remove MIPI; make mip.MSIP read-only 
The PRCI block outside the core will provide IPIs eventually
 2016-05-02 15:18:41 -07:00
Andrew Waterman 83fa489cef Stop using HTIF CSR port 
The port itself is still present to keep other stuff compiling.
 2016-05-02 14:40:52 -07:00
Andrew Waterman 491184a8f8 ERET -> xRET; remove mcfgaddr 2016-04-30 17:32:51 -07:00
Andrew Waterman 5af98145b9 don't signal bad physical address on TLB miss 2016-04-30 17:31:46 -07:00
Andrew Waterman cae4265f3b Change mcfgaddr pointer 2016-04-28 16:14:05 -07:00
Andrew Waterman 739cf07637 Remove mtime/mtimecmp 
The RTC is now a device that lives on the MMIO bus.
 2016-04-27 14:54:51 -07:00
Andrew Waterman fb5c38c186 Handle invalidate_lr in cache arbiter, not tile 2016-04-27 11:22:04 -07:00
Andrew Waterman b99db83e67 Avoid needless Vec generation 2016-04-27 00:28:39 -07:00
Andrew Waterman 8acec8eb36 Remove dead code from BTB 2016-04-27 00:28:12 -07:00
Andrew Waterman fe8c91f620 Fix IOMSHR state machine bug 
Sending the finish too early causes the CPU response to get dropped.

attn @zhemao
 2016-04-26 15:32:25 -07:00
Andrew Waterman 5fd5b58743 Remove stats CSR 2016-04-26 15:31:32 -07:00
Andrew Waterman d93677a343 Support larger cache sets when not using VM 2016-04-26 15:31:32 -07:00
Andrew Waterman 84fd45fd77 Pass TLB flush signal to I$ explicitly 2016-04-22 15:20:17 -07:00
Andrew Waterman 51e0870e23 Separate I$ and D$ interface signals that span clock cycles 
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
 2016-04-01 19:30:39 -07:00
Andrew Waterman dc662f28a0 Specify width on s1_pc to avoid width inference problem 2016-04-01 17:28:42 -07:00
Andrew Waterman 72f7f71eb5 No need to allow finishes to be sent in s_refill_resp state 
This is a hold-over from when writebacks needed finish messages.
 2016-04-01 16:19:57 -07:00
Andrew Waterman 37b9051762 No need to validate npc if BTB is disabled 2016-04-01 15:54:57 -07:00
Andrew Waterman 4480d1e817 Don't compile BTB when nEntries=0 2016-04-01 15:14:45 -07:00
Andrew Waterman d406dc1231 Remove vestigial BTB enable option 2016-04-01 15:14:34 -07:00
Andrew Waterman adb7eacf6e Fix Chisel3 build for XLen=32 2016-03-30 22:48:51 -07:00
Andrew Waterman 70664bbca0 Fix Chisel3 build for UseVM=false 2016-03-30 22:48:31 -07:00
Andrew Waterman 8ad8e8a691 Add partial Sv48/Sv57 support 
Right now, we don't support Sv39 and Sv48 at the same time, which needs
to change.
 2016-03-30 11:02:22 -07:00
Andrew Waterman e652821962 Use correct kind of TileLink arbiter 
It was "correct" before, but broke Chisel3 build.
 2016-03-28 22:53:47 -07:00
Andrew Waterman ed280fb3de Remove empty when statement (???) 2016-03-25 15:52:18 -07:00
Andrew Waterman 1ae6d09751 Slightly ameliorate D$->I$ critical path via scoreboard 2016-03-25 15:29:32 -07:00
Andrew Waterman a4685a073f Don't instantiate PTW when UseVM=false 2016-03-25 14:17:25 -07:00
Andrew Waterman 27b3cca046 Discover D$, PTW port counts dynamically 
This is a generator, after all...
 2016-03-25 14:16:56 -07:00
Andrew Waterman 8d1ba4d1ec Remove hard-coded XLEN values from D$ 2016-03-24 14:52:12 -07:00
Andrew Waterman 7ae44d4905 Add RV32 support 2016-03-10 17:32:00 -08:00
Andrew Waterman 82c595d11a Fix no-FPU elaboration of CSR file 2016-03-10 17:30:56 -08:00
Andrew Waterman bc15e8649e WIP on priv spec v1.9 2016-03-02 23:29:58 -08:00
Andrew Waterman 58fcc6b7c6 Get rid of useless mux 2016-01-28 11:44:59 -08:00
Andrew Waterman 52d6b0b1a5 Improve ALU QoR 
Rejigger muxes; share XOR gates between ADD/SUB, XOR, and BEQ.
 2016-01-20 17:42:31 -08:00
Andrew Waterman ae98af7077 don't mix SInt/UInt 2016-01-12 16:27:36 -08:00
Andrew Waterman 00d17abd78 Don't ignore data value when writing MIPI 2016-01-12 16:23:06 -08:00
Andrew Waterman 7bf503a275 Remove four integer/FP converters 2016-01-12 16:06:23 -08:00
Andrew Waterman 31d537c405 Add missing cloneType 2016-01-12 15:45:11 -08:00
Andrew Waterman e203b8b378 Make ALU generic for zscale 2015-11-24 19:17:07 -08:00
Andrew Waterman 5294e94794 Remove CSR back pressure ability 
We were using it for IPIs, but no longer need it.
 2015-11-24 18:28:14 -08:00
Andrew Waterman 4616db4695 Make RegFile/ImmGen usable by zscale 2015-11-24 18:27:07 -08:00
Andrew Waterman 6d1bf5c014 Use generic LoadGen/StoreGen 2015-11-24 18:13:33 -08:00
Andrew Waterman 0f092b9b59 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:51:43 -08:00
Andrew Waterman 2f515b2af6 Reduce critical path for fdiv valid signal 2015-11-06 23:28:31 -08:00
Andrew Waterman 833909a2b5 Chisel3 compatibility fixes 2015-09-30 14:36:26 -07:00
Andrew Waterman a7c908cb83 Don't declare Reg inside of when 
We haven't yet decided what the Chisel3 semantics for this will be.
 2015-09-30 12:43:36 -07:00
Andrew Waterman f8a7a80644 Make perf counters optional 2015-09-28 13:55:23 -07:00
Andrew Waterman 5e88ead984 Add pseudo-ops to instructions.scala 2015-09-28 11:52:27 -07:00
Andrew Waterman b93a94597c Remove needless control logic 2015-09-27 13:31:52 -07:00
Andrew Waterman c3fff12ff0 Revert "replace remaining uses of Vec.fill" 
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
 2015-09-25 17:09:06 -07:00
Andrew Waterman 0bfb2962a6 Assume coh.isRead returns true for store-conditional 
This requires an uncore update.
 2015-09-25 15:26:11 -07:00
Andrew Waterman e72e5a34b5 Fix storage of SP values in DP registers 
The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s.  This meant that an FSD + FLD of that register
would not restore the value properly.

Also, minor code cleanup.
 2015-09-21 12:20:44 -07:00
Andrew Waterman 78b2e947de Chisel3 compatibility fixes 2015-09-11 15:43:07 -07:00
Andrew Waterman 1718333f83 Don't use Vec as lvalue 2015-08-05 15:29:33 -07:00
Andrew Waterman 546205b174 Chisel3 compatibility: use >>Int instead of >>UInt 2015-08-05 15:29:03 -07:00
Andrew Waterman fb5524372d bump scala to 2.11.6 2015-08-03 19:51:08 -07:00
Andrew Waterman d4c94c6566 Chisel3 has different Vec semantics 
Vec(a, b) := c doesn't modify a and b in chisel3.
 2015-08-03 19:08:00 -07:00
Andrew Waterman c345d72af4 Chisel3: Flip order of := and <> 2015-08-03 18:53:09 -07:00
Andrew Waterman ef319edc84 Bits -> UInt 2015-08-02 21:03:42 -07:00
Andrew Waterman 52fc34a138 Chisel3: bulk connect is not commutative 
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
 2015-08-01 21:11:25 -07:00
Andrew Waterman 6c0e1e33ab Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
Andrew Waterman 6d7cc37e87 Specify some uninferrable widths 
It's really scary that Chisel2 passed this stuff.
 2015-07-31 14:23:52 -07:00
Andrew Waterman 45cf64dbd7 Use UInt instead of Vec[Bool] 2015-07-31 04:59:45 -07:00
Andrew Waterman 57930e8a26 Chisel3 compatibility potpourri 2015-07-30 23:53:02 -07:00
Andrew Waterman ce161b83e3 Chisel3 compatibility: avoid subword assignment 2015-07-29 15:03:13 -07:00
Andrew Waterman c8c312e860 minor btb cleanup 2015-07-29 15:03:01 -07:00
Andrew Waterman a2fdcdcaef Use Seq, not Iterable, when traversal order matters 2015-07-29 00:24:58 -07:00
Andrew Waterman 431dd2219b Another Bits -> BitPat 2015-07-28 20:13:56 -07:00
Andrew Waterman 049fc8dc24 Chisel3 compatibility: use BitPat for don't-cares 
This one's hella ugly, but for the time being, idgaf.
 2015-07-28 02:48:49 -07:00
Andrew Waterman f2dcc40e67 Chisel3 compatibility changes 2015-07-27 12:42:20 -07:00
Andrew Waterman ae73e3a997 Only instantiate div/sqrt unit if requested 2015-07-22 22:18:18 -07:00
Andrew Waterman e9433ee01e Minor cleanup 2015-07-22 17:38:08 -07:00
Andrew Waterman b4e4ceed3d Factor out some more hazard detection code 2015-07-22 15:52:13 -07:00
Andrew Waterman bd785e7d19 Factor out common hazard detection code 2015-07-22 15:46:20 -07:00
Andrew Waterman cc447c8110 Refactor pipeline RTL (merge ctrl + dpath into rocket) 2015-07-21 17:10:56 -07:00
Andrew Waterman ac6e73e317 Add Wire() wrap 2015-07-15 20:24:18 -07:00
Andrew Waterman 5b7f3c3006 Don't use clone 2015-07-15 17:30:50 -07:00
Andrew Waterman be2ff6dec7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:33:46 -07:00
Andrew Waterman a78e28523c Chisel3: Don't mix Mux types 2015-07-11 14:06:08 -07:00
Andrew Waterman 3233867390 Use Chisel3 SeqMem construct 2015-07-11 13:34:57 -07:00
Andrew Waterman 5362e2bbbd New machine-mode timer facility 2015-07-05 16:38:49 -07:00
Andrew Waterman 5e009ecc75 Fix an apparently benign PC sign-extension bug 2015-06-11 16:08:39 -07:00
Andrew Waterman 6a9390c50e Avoid spurious D$ assertion failures 
For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
 2015-05-19 03:00:53 -07:00
Andrew Waterman f460cb6c54 Update to privileged architecture 1.7 2015-05-19 02:32:21 -07:00
Andrew Waterman 254498042a Fix Split for 0-width wires 2015-05-18 18:23:17 -07:00
Andrew Waterman d31b26c342 Clean up handling of icache's io.cpu.npc signal 2015-05-18 18:22:48 -07:00
Andrew Waterman 9ade0e41cc Integrate divide/sqrt unit 2015-04-04 16:39:17 -07:00
Andrew Waterman fe27b9b1b2 Support writing sstatus.fs even without an FPU 2015-04-04 15:20:18 -07:00
Andrew Waterman bce62d5774 Update PTE format to reflect reserved bits 2015-04-04 15:19:15 -07:00
Andrew Waterman d912ea265e New virtual memory implementation (Sv39) 2015-03-27 16:20:59 -07:00
Andrew Waterman faada5f110 Mask off LSBs of sepc/mepc/stvec 
Therefore, they cannot generate misaligned instruction exceptions.
When a misaligned instruction exception does occur, mbadaddr
retains the misaligned PC bits, so no information is actually lost.
 2015-03-25 00:20:58 -07:00
Andrew Waterman 543ac91cf2 Misaligned fetches can't happen at the I$ anymore 
They are caught before the I$ ever sees them, so leverage that fact.
 2015-03-24 23:55:43 -07:00
Andrew Waterman 90b31586ff Misc. CSR fixes/improvements 
- Support RV32 mstatus register
- Don't ignore mstatus.stie bit
- Support custom M-mode R/W CSRs for Raven chip
 2015-03-24 23:50:18 -07:00
Andrew Waterman 822698b567 support disabling supervisor mode (via UseVM parameter) 2015-03-24 19:32:45 -07:00
Andrew Waterman 0332c1e7fe Reduce latency of page table walks 
A small cache in the PTW caches non-leaf PTEs, reducing latency and D$ misses.
 2015-03-24 18:58:38 -07:00