riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Remove needless control logic

Browse Source
This commit is contained in:
Andrew Waterman 2015-09-27 13:31:52 -07:00
parent 4bda6b6757
commit b93a94597c
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/nbdcache.scala
View File

@ -1016,7 +1016,7 @@ class HellaCache extends L1HellaCacheModule {
val cache_resp = Wire(Valid(new HellaCacheResp))
cache_resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
cache_resp.bits := s2_req
cache_resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
cache_resp.bits.has_data := isRead(s2_req.cmd)
cache_resp.bits.data := loadgen.byte | s2_sc_fail
cache_resp.bits.store_data := s2_req.data
cache_resp.bits.nack := s2_valid && s2_nack