riscv/rocket-chip
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Fix Chisel3 build for XLen=32

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This commit is contained in:
Andrew Waterman 2016-03-30 22:48:51 -07:00
parent 70664bbca0
commit adb7eacf6e
2 changed files with 11 additions and 7 deletions
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14
rocket/src/main/scala/csr.scala
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@ -357,15 +357,17 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
io.status.sd_rv32 := io.status.sd
when (io.exception || csr_xcpt) {
val ldst_badaddr = {
val (upper, lower) = Split(io.rw.wdata, vaddrBits)
val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
Cat(sign, lower)
}
def compressVAddr(addr: UInt) =
if (vaddrBitsExtended == vaddrBits) addr
else {
val (upper, lower) = Split(addr, vaddrBits)
val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
Cat(sign, lower)
}
val ldst =
cause === Causes.fault_load || cause === Causes.misaligned_load ||
cause === Causes.fault_store || cause === Causes.misaligned_store
val badaddr = Mux(ldst, ldst_badaddr, io.pc)
val badaddr = Mux(ldst, compressVAddr(io.rw.wdata), io.pc)
val epc = ~(~io.pc | (coreInstBytes-1))
val pie = read_mstatus(reg_mstatus.prv)

4
rocket/src/main/scala/util.scala
View File

@ -14,7 +14,9 @@ object Util {
implicit def seqToVec[T <: Data](x: Seq[T]): Vec[T] = Vec(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit def sextToConv(x: UInt) = new AnyRef {
def sextTo(n: Int): UInt = Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
def sextTo(n: Int): UInt =
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
implicit def intToUnsigned(x: Int): Unsigned = new Unsigned(x)