Pass TLB flush signal to I$ explicitly
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@ -23,7 +23,8 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val btb_update = Valid(new BTBUpdate)
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val bht_update = Valid(new BHTUpdate)
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val ras_update = Valid(new RASUpdate)
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val invalidate = Bool(OUTPUT)
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val flush_icache = Bool(OUTPUT)
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val flush_tlb = Bool(OUTPUT)
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val npc = UInt(INPUT, width = vaddrBitsExtended)
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}
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@ -80,7 +81,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update := io.cpu.ras_update
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btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
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btb.io.invalidate := io.cpu.flush_icache || io.cpu.flush_tlb // virtual tags
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when (!stall && !icmiss) {
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btb.io.req.valid := true
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s2_btb_resp_valid := btb.io.resp.valid
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@ -103,7 +104,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
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io.mem <> icache.io.mem
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icache.io.req.valid := !stall && !s0_same_block
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icache.io.req.bits.idx := io.cpu.npc
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icache.io.invalidate := io.cpu.invalidate
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icache.io.invalidate := io.cpu.flush_icache
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icache.io.s1_ppn := tlb.io.resp.ppn
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icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.ptw.invalidate
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@ -496,7 +496,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret
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Mux(replay_wb, wb_reg_pc, // replay
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mem_npc)).toUInt // mispredicted branch
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io.imem.invalidate := wb_reg_valid && wb_ctrl.fence_i
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io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i
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io.imem.flush_tlb := csr.io.fatc
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io.imem.resp.ready := !ctrl_stalld || csr.io.interrupt
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io.imem.btb_update.valid := mem_reg_valid && !mem_npc_misaligned && mem_wrong_npc && mem_cfi_taken && !take_pc_wb
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