riscv/rocket-chip
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Pipeline D$->I$ control paths

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These stretch the miss latency by a cycle in exchange for slack.
The current implementation also adds a cycle to mul/div latency,
which can be worked around for more hardware (possibly gated by
the FastMulDiv option).
This commit is contained in:
Andrew Waterman 2016-05-13 17:07:28 -07:00
parent 8fa2de0816
commit 742c05d6a7
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/rocket.scala
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@ -450,7 +450,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
val sboard = new Scoreboard(32)
sboard.clear(ll_wen, ll_waddr)
val id_sboard_hazard = checkHazards(hazard_targets, sboard.readBypassed _)
val id_sboard_hazard = checkHazards(hazard_targets, sboard.read _)
sboard.set(wb_set_sboard && wb_wen, wb_waddr)
// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.
@ -486,7 +486,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
id_ctrl.fp && id_stall_fpu ||
id_ctrl.mem && !io.dmem.req.ready ||
id_ctrl.mem && Reg(next = !io.dmem.req.ready) ||
Bool(usingRoCC) && wb_reg_rocc_pending && id_ctrl.rocc && !io.rocc.cmd.ready ||
id_do_fence ||
csr.io.csr_stall