Remove MIPI; make mip.MSIP read-only
The PRCI block outside the core will provide IPIs eventually
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@ -144,7 +144,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val reg_mie = Reg(init=UInt(0, xLen))
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val reg_mideleg = Reg(init=UInt(0, xLen))
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val reg_medeleg = Reg(init=UInt(0, xLen))
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val reg_mip = Reg(init=new MIP().fromBits(0))
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val reg_mip = Reg(new MIP)
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val reg_mepc = Reg(UInt(width = vaddrBitsExtended))
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val reg_mcause = Reg(Bits(width = xLen))
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val reg_mbadaddr = Reg(UInt(width = vaddrBitsExtended))
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@ -201,7 +201,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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CSRs.misa -> UInt(isa),
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CSRs.mstatus -> read_mstatus,
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CSRs.mtvec -> reg_mtvec,
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CSRs.mipi -> reg_mip.msip,
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CSRs.mip -> read_mip,
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CSRs.mie -> reg_mie,
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CSRs.mideleg -> reg_mideleg,
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@ -415,10 +414,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_mip.ssip := new_mip.ssip
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reg_mip.stip := new_mip.stip
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}
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reg_mip.msip := new_mip.msip
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}
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when (decoded_addr(CSRs.mipi)) {
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reg_mip.msip := wdata(0)
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}
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when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts }
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when (decoded_addr(CSRs.mepc)) { reg_mepc := ~(~wdata | (coreInstBytes-1)) }
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