Handle invalidate_lr in cache arbiter, not tile

rocket/src/main/scala/arbiter.scala

@@ -16,6 +16,7 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
 
   val r_valid = io.requestor.map(r => Reg(next=r.req.valid))
 
+  io.mem.invalidate_lr := io.requestor.map(_.invalidate_lr).reduce(_||_)
   io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
   io.requestor(0).req.ready := io.mem.req.ready
   for (i <- 1 until n)

rocket/src/main/scala/ptw.scala

@@ -120,6 +120,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
   io.mem.req.bits.addr := pte_addr
   io.mem.s1_data := pte_wdata.toBits
   io.mem.s1_kill := Bool(false)
+  io.mem.invalidate_lr := Bool(false)
   
   val r_resp_ppn = io.mem.req.bits.addr >> pgIdxBits
   val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count)

rocket/src/main/scala/tile.scala

@@ -47,7 +47,6 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
   val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
   val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
   val cachedPorts = collection.mutable.ArrayBuffer(dcache.io.mem)
-  dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
   io.host <> core.io.host
   icache.io.cpu <> core.io.imem