Chisel3 compatibility potpourri
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@ -306,7 +306,7 @@ class CSRFile extends CoreModule
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reg_mstatus.prv2 := reg_mstatus.prv1
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reg_mstatus.ie2 := reg_mstatus.ie1
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reg_mepc := io.pc & SInt(-coreInstBytes)
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reg_mepc := ~(~io.pc | (coreInstBytes-1))
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reg_mcause := io.cause
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when (csr_xcpt) {
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reg_mcause := Causes.illegal_instruction
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@ -439,7 +439,7 @@ class FPU extends Module
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val divSqrt_in_flight = Reg(init=Bool(false))
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// writeback arbitration
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case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, wdata: Bits, wexc: Bits)
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case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, wdata: UInt, wexc: UInt)
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val pipes = List(
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Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits.data, fpmu.io.out.bits.exc),
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Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits.data, ifpu.io.out.bits.exc),
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@ -50,7 +50,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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val tlb = Module(new TLB)
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val s1_pc_ = Reg(UInt())
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val s1_pc = s1_pc_ & SInt(-coreInstBytes) // discard PC LSBS (this propagates down the pipeline)
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val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
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val s1_same_block = Reg(Bool())
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val s2_valid = Reg(init=Bool(true))
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val s2_pc = Reg(init=UInt(START_ADDR))
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@ -85,7 +85,7 @@ class PTW(n: Int) extends CoreModule
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val (pte_cache_hit, pte_cache_data) = {
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val size = log2Up(pgLevels * 2)
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val plru = new PseudoLRU(size)
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val valid = Reg(init=Vec(Bool(), size))
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val valid = Reg(Vec(Bool(), size))
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val validBits = valid.toBits
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val tags = Mem(UInt(width = paddrBits), size)
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val data = Mem(UInt(width = ppnBits), size)
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@ -158,7 +158,7 @@ class TLB extends TLBModule {
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val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm
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val bad_va = io.req.bits.vpn(vpnBits) != io.req.bits.vpn(vpnBits-1)
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// it's only a store hit if the dirty bit is set
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val tag_hits = tag_cam.io.hits & (dirty_array.toBits | ~(io.req.bits.store.toSInt & w_array))
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val tag_hits = tag_cam.io.hits & (dirty_array.toBits | ~Mux(io.req.bits.store, w_array, UInt(0)))
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val tag_hit = tag_hits.orR
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val tlb_hit = vm_enabled && tag_hit
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val tlb_miss = vm_enabled && !tag_hit && !bad_va
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