Vec(Reg) -> Reg(Vec)
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@ -36,7 +36,7 @@ class RAS(nras: Int) {
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private val count = Reg(init=UInt(0,log2Up(nras+1)))
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private val pos = Reg(init=UInt(0,log2Up(nras)))
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private val stack = Vec.fill(nras){Reg(UInt())}
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private val stack = Reg(Vec.fill(nras){UInt()})
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}
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class BHTResp extends Bundle with BTBParameters {
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@ -23,9 +23,9 @@ class Datapath extends CoreModule
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val ex_reg_pc = Reg(UInt())
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val ex_reg_inst = Reg(Bits())
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val ex_reg_kill = Reg(Bool())
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val ex_reg_rs_bypass = Vec.fill(2)(Reg(Bool()))
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val ex_reg_rs_lsb = Vec.fill(2)(Reg(Bits()))
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val ex_reg_rs_msb = Vec.fill(2)(Reg(Bits()))
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val ex_reg_rs_bypass = Reg(Vec.fill(2)(Bool()))
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val ex_reg_rs_lsb = Reg(Vec.fill(2)(Bits()))
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val ex_reg_rs_msb = Reg(Vec.fill(2)(Bits()))
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// memory definitions
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val mem_reg_pc = Reg(UInt())
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@ -461,7 +461,7 @@ class FPU extends Module
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val memLatencyMask = latencyMask(mem_ctrl, 2)
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val wen = Reg(init=Bits(0, maxLatency-1))
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val winfo = Vec.fill(maxLatency-1){Reg(Bits())}
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val winfo = Reg(Vec.fill(maxLatency-1){Bits()})
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val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
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val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, ex_reg_valid)
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val mem_winfo = Cat(pipeid(mem_ctrl), mem_reg_inst(11,7))
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@ -218,7 +218,7 @@ class ICache extends FrontendModule
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val s1_tag_match = Vec.fill(nWays){Bool()}
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val s2_tag_hit = Vec.fill(nWays){Bool()}
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val s2_dout = Vec.fill(nWays){Reg(Bits())}
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val s2_dout = Reg(Vec.fill(nWays){Bits()})
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for (i <- 0 until nWays) {
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val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool
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@ -749,7 +749,7 @@ class HellaCache extends L1HellaCacheModule {
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val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
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for (w <- 0 until nWays) {
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val regs = Vec.fill(rowWords){Reg(Bits(width = encDataBits))}
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val regs = Reg(Vec.fill(rowWords){Bits(width = encDataBits)})
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val en1 = s1_clk_en && s1_tag_eq_way(w)
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for (i <- 0 until regs.size) {
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val en = en1 && ((Bool(i == 0) || !Bool(doNarrowRead)) || s1_writeback)
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@ -62,7 +62,7 @@ class AccumulatorExample extends RoCC
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{
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val n = 4
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val regfile = Mem(UInt(width = xLen), n)
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val busy = Vec.fill(n){Reg(init=Bool(false))}
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val busy = Reg(init=Vec.fill(n){Bool(false)})
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val cmd = Queue(io.cmd)
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val funct = cmd.bits.inst.funct
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