Chisel3 compatibility fixes
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a7c908cb83
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833909a2b5
@ -69,7 +69,7 @@ class BHT(nbht: Int) {
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when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) }
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}
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private val table = Mem(UInt(width = 2), nbht)
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private val table = Mem(nbht, UInt(width = 2))
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val history = Reg(UInt(width = nbhtbits))
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}
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@ -134,18 +134,18 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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}
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val idxValid = Reg(init=UInt(0, entries))
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val idxs = Mem(UInt(width=matchBits), entries)
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val idxPages = Mem(UInt(width=log2Up(nPages)), entries)
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val tgts = Mem(UInt(width=matchBits), entries)
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val tgtPages = Mem(UInt(width=log2Up(nPages)), entries)
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val pages = Mem(UInt(width=vaddrBits-matchBits), nPages)
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val idxs = Mem(entries, UInt(width=matchBits))
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val idxPages = Mem(entries, UInt(width=log2Up(nPages)))
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val tgts = Mem(entries, UInt(width=matchBits))
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val tgtPages = Mem(entries, UInt(width=log2Up(nPages)))
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val pages = Mem(nPages, UInt(width=vaddrBits-matchBits))
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val pageValid = Reg(init=UInt(0, nPages))
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val idxPagesOH = idxPages.map(UIntToOH(_)(nPages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(nPages-1,0))
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val useRAS = Reg(Vec(Bool(), entries))
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val isJump = Reg(Vec(Bool(), entries))
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val brIdx = Mem(UInt(width=log2Up(params(FetchWidth))), entries)
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val useRAS = Reg(Vec(entries, Bool()))
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val isJump = Reg(Vec(entries, Bool()))
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val brIdx = Mem(entries, UInt(width=log2Up(params(FetchWidth))))
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private def page(addr: UInt) = addr >> matchBits
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private def pageMatch(addr: UInt) = {
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@ -382,7 +382,7 @@ class FPU extends CoreModule
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val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1, 32), rec_s), rec_d)
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// regfile
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val regfile = Mem(Bits(width = 65), 32)
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val regfile = Mem(32, Bits(width = 65))
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when (load_wb) {
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regfile(load_wb_tag) := load_wb_data_recoded
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if (EnableCommitLog) {
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@ -387,7 +387,7 @@ class MSHRFile extends L1HellaCacheModule {
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val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))
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val sdq_rdy = !sdq_val.andR
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val sdq_enq = io.req.valid && io.req.ready && cacheable && isWrite(io.req.bits.cmd)
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val sdq = Mem(io.req.bits.data, sdqDepth)
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val sdq = Mem(sdqDepth, io.req.bits.data)
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when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
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val idxMatch = Wire(Vec(Bool(), nMSHRs))
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@ -87,8 +87,8 @@ class PTW(n: Int) extends CoreModule
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val plru = new PseudoLRU(size)
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val valid = Reg(Vec(Bool(), size))
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val validBits = valid.toBits
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val tags = Mem(UInt(width = paddrBits), size)
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val data = Mem(UInt(width = ppnBits), size)
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val tags = Mem(size, UInt(width = paddrBits))
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val data = Mem(size, UInt(width = ppnBits))
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val hits = Vec(tags.map(_ === pte_addr)).toBits & validBits
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val hit = hits.orR
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@ -571,7 +571,7 @@ class Rocket extends CoreModule
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}
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class RegFile {
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private val rf = Mem(UInt(width = 64), 31)
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private val rf = Mem(31, UInt(width = 64))
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private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]()
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private var canRead = true
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def read(addr: UInt) = {
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@ -33,7 +33,7 @@ class CAMIO extends TLBBundle {
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class RocketCAM extends TLBModule {
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val io = new CAMIO
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val cam_tags = Mem(Bits(width = camTagBits), entries)
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val cam_tags = Mem(entries, Bits(width = camTagBits))
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val vb_array = Reg(init=Bits(0, entries))
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when (io.write) {
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@ -109,7 +109,7 @@ class TLB extends TLBModule {
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val r_req = Reg(new TLBReq)
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val tag_cam = Module(new RocketCAM)
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val tag_ram = Mem(io.ptw.resp.bits.pte.ppn, entries)
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val tag_ram = Mem(entries, io.ptw.resp.bits.pte.ppn)
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val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
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tag_cam.io.tag := lookup_tag
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