Fix Chisel3 build for UseVM=false
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@ -83,14 +83,14 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
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val ptw = new TLBPTWIO
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}
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val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
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val r_refill_tag = Reg(UInt())
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val r_refill_waddr = Reg(UInt())
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val r_req = Reg(new TLBReq)
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val tag_cam = Module(new RocketCAM)
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val tag_ram = Mem(entries, io.ptw.resp.bits.pte.ppn)
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val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
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val r_refill_tag = Reg(tag_cam.io.write_tag)
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val r_refill_waddr = Reg(tag_cam.io.write_addr)
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val r_req = Reg(new TLBReq)
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val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
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tag_cam.io.tag := lookup_tag
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