Purge UInt := SInt assignments

rocket/src/main/scala/csr.scala

@@ -291,9 +291,9 @@ class CSRFile extends CoreModule
   io.csr_xcpt := csr_xcpt
   io.eret := insn_ret || insn_redirect_trap
   io.status := reg_mstatus
-  io.status.fs := reg_mstatus.fs.orR.toSInt // either off or dirty (no clean/initial support yet)
-  io.status.xs := reg_mstatus.xs.orR.toSInt // either off or dirty (no clean/initial support yet)
-  io.status.sd := reg_mstatus.xs.orR || reg_mstatus.fs.orR
+  io.status.fs := Fill(2, reg_mstatus.fs.orR) // either off or dirty (no clean/initial support yet)
+  io.status.xs := Fill(2, reg_mstatus.xs.orR) // either off or dirty (no clean/initial support yet)
+  io.status.sd := io.status.fs.andR || io.status.xs.andR
   if (xLen == 32)
     io.status.sd_rv32 := io.status.sd
 
@@ -405,7 +405,7 @@ class CSRFile extends CoreModule
     when (decoded_addr(CSRs.fflags))   { reg_fflags := wdata }
     when (decoded_addr(CSRs.frm))      { reg_frm := wdata }
     when (decoded_addr(CSRs.fcsr))     { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
-    when (decoded_addr(CSRs.mepc))     { reg_mepc := wdata(vaddrBitsExtended-1,0).toSInt & SInt(-coreInstBytes) }
+    when (decoded_addr(CSRs.mepc))     { reg_mepc := ~(~wdata | (coreInstBytes-1)) }
     when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
     when (decoded_addr(CSRs.mcause))   { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
     when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata(vaddrBitsExtended-1,0) }
@@ -436,8 +436,8 @@ class CSRFile extends CoreModule
       }
       when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
       when (decoded_addr(CSRs.sptbr))    { reg_sptbr := Cat(wdata(paddrBits-1, pgIdxBits), Bits(0, pgIdxBits)) }
-      when (decoded_addr(CSRs.sepc))     { reg_sepc := wdata(vaddrBitsExtended-1,0).toSInt & SInt(-coreInstBytes) }
-      when (decoded_addr(CSRs.stvec))    { reg_stvec := wdata(vaddrBits-1,0).toSInt & SInt(-coreInstBytes) }
+      when (decoded_addr(CSRs.sepc))     { reg_sepc := ~(~wdata | (coreInstBytes-1)) }
+      when (decoded_addr(CSRs.stvec))    { reg_stvec := ~(~wdata | (coreInstBytes-1)) }
     }
   }
 

rocket/src/main/scala/fpu.scala

@@ -228,7 +228,7 @@ class FPToInt extends Module
     io.out.bits.exc := dcmp_exc
   }
   when (in.cmd === FCMD_CVT_IF) {
-    io.out.bits.toint := Mux(in.typ(1), d2i._1, d2i._1(31,0).toSInt)
+    io.out.bits.toint := Mux(in.typ(1), d2i._1, d2i._1(31,0).toSInt).toUInt
     io.out.bits.exc := d2i._2
   }
 

rocket/src/main/scala/multiplier.scala

@@ -95,7 +95,7 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false) extends Module {
       !isHi && (mplier & ~eOutMask) === UInt(0)
     val eOutRes = (mulReg >> (mulw - count * mulUnroll)(log2Up(mulw)-1,0))
     val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
-    remainder := Cat(nextMulReg1 >> w, Bool(false), nextMulReg1(w-1,0)).toSInt
+    remainder := Cat(nextMulReg1 >> w, Bool(false), nextMulReg1(w-1,0))
 
     count := count + 1
     when (eOut || count === mulw/mulUnroll-1) {

rocket/src/main/scala/nbdcache.scala

@@ -705,7 +705,7 @@ class HellaCache extends L1HellaCacheModule {
   // data read for new requests
   readArb.io.in(3).valid := io.cpu.req.valid
   readArb.io.in(3).bits.addr := io.cpu.req.bits.addr
-  readArb.io.in(3).bits.way_en := SInt(-1)
+  readArb.io.in(3).bits.way_en := ~UInt(0, nWays)
   when (!readArb.io.in(3).ready) { io.cpu.req.ready := Bool(false) }
 
   // recycled requests
@@ -713,7 +713,7 @@ class HellaCache extends L1HellaCacheModule {
   metaReadArb.io.in(0).bits.idx := s2_req.addr >> blockOffBits
   readArb.io.in(0).valid := s2_recycle
   readArb.io.in(0).bits.addr := s2_req.addr
-  readArb.io.in(0).bits.way_en := SInt(-1)
+  readArb.io.in(0).bits.way_en := ~UInt(0, nWays)
 
   // tag check and way muxing
   def wayMap[T <: Data](f: Int => T) = Vec((0 until nWays).map(f))
@@ -800,7 +800,7 @@ class HellaCache extends L1HellaCacheModule {
   // replays
   readArb.io.in(1).valid := mshrs.io.replay.valid
   readArb.io.in(1).bits := mshrs.io.replay.bits
-  readArb.io.in(1).bits.way_en := SInt(-1)
+  readArb.io.in(1).bits.way_en := ~UInt(0, nWays)
   mshrs.io.replay.ready := readArb.io.in(1).ready
   s1_replay := mshrs.io.replay.valid && readArb.io.in(1).ready
   metaReadArb.io.in(1) <> mshrs.io.meta_read
@@ -828,7 +828,7 @@ class HellaCache extends L1HellaCacheModule {
   writeArb.io.in(1).valid := narrow_grant.valid && narrow_grant.bits.hasData()
   writeArb.io.in(1).bits.addr := mshrs.io.refill.addr
   writeArb.io.in(1).bits.way_en := mshrs.io.refill.way_en
-  writeArb.io.in(1).bits.wmask := SInt(-1)
+  writeArb.io.in(1).bits.wmask := ~UInt(0, nWays)
   writeArb.io.in(1).bits.data := narrow_grant.bits.data(encRowBits-1,0)
   readArb.io.out.ready := !narrow_grant.valid || narrow_grant.ready // insert bubble if refill gets blocked
   readArb.io.out <> data.io.read

rocket/src/main/scala/rocket.scala

@@ -198,7 +198,7 @@ class Rocket extends CoreModule
   alu.io.dw := ex_ctrl.alu_dw
   alu.io.fn := ex_ctrl.alu_fn
   alu.io.in2 := ex_op2.toUInt
-  alu.io.in1 := ex_op1
+  alu.io.in1 := ex_op1.toUInt
   
   // multiplier and divider
   val div = Module(new MulDiv(mulUnroll = if(params(FastMulDiv)) 8 else 1,

rocket/src/main/scala/tlb.scala

@@ -178,7 +178,7 @@ class TLB extends TLBModule {
   // clear invalid entries on access, or all entries on a TLB flush
   tag_cam.io.clear := io.ptw.invalidate || io.req.fire()
   tag_cam.io.clear_mask := ~valid_array.toBits | (tag_cam.io.hits & ~tag_hits)
-  when (io.ptw.invalidate) { tag_cam.io.clear_mask := SInt(-1) }
+  when (io.ptw.invalidate) { tag_cam.io.clear_mask := ~UInt(0, entries) }
   
   io.ptw.req.valid := state === s_request
   io.ptw.req.bits.addr := r_refill_tag