Rename PRCICoreIO to PRCITileIO
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000e20f937
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@ -76,7 +76,7 @@ object CSR
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}
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class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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val prci = new PRCICoreIO().flip
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val prci = new PRCITileIO().flip
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val rw = new Bundle {
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val addr = UInt(INPUT, CSR.ADDRSZ)
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val cmd = Bits(INPUT, CSR.SZ)
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@ -110,7 +110,7 @@ object ImmGen {
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class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val prci = new PRCICoreIO().flip
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val prci = new PRCITileIO().flip
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val imem = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
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val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
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val ptw = new DatapathPTWIO().flip
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@ -31,7 +31,7 @@ abstract class Tile(resetSignal: Bool = null)
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val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
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val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
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val host = new HtifIO // Unused, but temporarily extant for zscale/groundtest
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val prci = new PRCICoreIO().flip
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val prci = new PRCITileIO().flip
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val dma = new DmaIO
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}
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}
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