Remove HTIF port
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@ -30,7 +30,6 @@ abstract class Tile(resetSignal: Bool = null)
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val io = new Bundle {
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val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
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val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
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val host = new HtifIO // Unused, but temporarily extant for zscale/groundtest
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val prci = new PRCITileIO().flip
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val dma = new DmaIO
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}
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@ -142,9 +141,4 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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fpu.io.cp_resp.ready := Bool(false)
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}
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}
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// TODO remove
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io.host.csr.resp.valid := io.host.csr.req.valid
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io.host.csr.req.ready := io.host.csr.resp.ready
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io.host.csr.resp.bits := UInt(0)
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}
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