support disabling supervisor mode (via UseVM parameter)
This commit is contained in:
Andrew Waterman
parent
0332c1e7fe
commit
822698b567
@ -170,10 +170,56 @@ class CSRFile extends CoreModule
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io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
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val read_mstatus = io.status.toBits
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val read_sstatus = new SStatus
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read_sstatus := new SStatus().fromBits(read_mstatus) // sstatus mostly overlaps mstatus
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read_sstatus.zero0 := 0
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read_sstatus.zero1 := 0
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read_sstatus.zero2 := 0
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read_sstatus.zero3 := 0
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read_sstatus.zero4 := 0
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read_sstatus.zero5 := 0
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read_sstatus.ua := io.status.ua
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read_sstatus.tip := r_irq_timer
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val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
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CSRs.fflags -> (if (!params(BuildFPU).isEmpty) reg_fflags else UInt(0)),
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CSRs.frm -> (if (!params(BuildFPU).isEmpty) reg_frm else UInt(0)),
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CSRs.fcsr -> (if (!params(BuildFPU).isEmpty) Cat(reg_frm, reg_fflags) else UInt(0)),
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CSRs.cycle -> reg_time,
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CSRs.scycle -> reg_time,
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CSRs.time -> reg_time,
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CSRs.stime -> reg_time,
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CSRs.instret -> reg_instret,
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CSRs.sinstret -> reg_instret,
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CSRs.mstatus -> read_mstatus,
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CSRs.mscratch -> reg_mscratch,
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CSRs.mepc -> reg_mepc,
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CSRs.mbadaddr -> reg_mbadaddr,
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CSRs.mcause -> reg_mcause,
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CSRs.stimecmp -> reg_stimecmp,
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CSRs.stvec -> reg_stvec,
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CSRs.hartid -> io.host.id,
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CSRs.send_ipi -> io.host.id, /* don't care */
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CSRs.stats -> reg_stats,
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CSRs.tohost -> reg_tohost,
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CSRs.fromhost -> reg_fromhost)
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if (params(UseVM)) {
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read_mapping += CSRs.sstatus -> read_sstatus.toBits
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read_mapping += CSRs.sscratch -> reg_sscratch
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read_mapping += CSRs.scause -> reg_scause
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read_mapping += CSRs.sbadaddr -> reg_sbadaddr
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read_mapping += CSRs.sptbr -> reg_sptbr
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read_mapping += CSRs.sasid -> UInt(0)
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read_mapping += CSRs.sepc -> reg_sepc
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}
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for (i <- 0 until reg_uarch_counters.size)
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read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
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val addr = Mux(cpu_ren, io.rw.addr, host_pcr_bits.addr)
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val decoded_addr = Map((
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for ((v, i) <- CSRs.all.zipWithIndex)
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yield v -> (addr === CSRs.all(i))):_*)
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val decoded_addr = read_mapping map { case (k, v) => k -> (addr === k) }
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val addr_valid = decoded_addr.values.reduce(_||_)
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val fp_csr = decoded_addr(CSRs.fflags) || decoded_addr(CSRs.frm) || decoded_addr(CSRs.fcsr)
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@ -268,50 +314,6 @@ class CSRFile extends CoreModule
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when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.tohost)) { reg_tohost := UInt(0) }
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val read_mstatus = io.status.toBits
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val read_sstatus = new SStatus
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read_sstatus := new SStatus().fromBits(read_mstatus) // sstatus mostly overlaps mstatus
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read_sstatus.zero0 := 0
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read_sstatus.zero1 := 0
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read_sstatus.zero2 := 0
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read_sstatus.zero3 := 0
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read_sstatus.zero4 := 0
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read_sstatus.zero5 := 0
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read_sstatus.ua := io.status.ua
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read_sstatus.tip := r_irq_timer
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val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
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CSRs.fflags -> (if (!params(BuildFPU).isEmpty) reg_fflags else UInt(0)),
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CSRs.frm -> (if (!params(BuildFPU).isEmpty) reg_frm else UInt(0)),
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CSRs.fcsr -> (if (!params(BuildFPU).isEmpty) Cat(reg_frm, reg_fflags) else UInt(0)),
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CSRs.cycle -> reg_time,
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CSRs.time -> reg_time,
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CSRs.scycle -> reg_time,
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CSRs.stime -> reg_time,
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CSRs.instret -> reg_instret,
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CSRs.sinstret -> reg_instret,
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CSRs.mstatus -> read_mstatus,
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CSRs.mscratch -> reg_mscratch,
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CSRs.mepc -> reg_mepc,
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CSRs.mbadaddr -> reg_mbadaddr,
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CSRs.mcause -> reg_mcause,
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CSRs.sstatus -> read_sstatus.toBits,
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CSRs.sscratch -> reg_sscratch,
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CSRs.sepc -> reg_sepc,
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CSRs.scause -> reg_scause,
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CSRs.sbadaddr -> reg_sbadaddr,
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CSRs.sptbr -> reg_sptbr,
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CSRs.sasid -> UInt(0),
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CSRs.stimecmp -> reg_stimecmp,
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CSRs.stvec -> reg_stvec,
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CSRs.hartid -> io.host.id,
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CSRs.stats -> reg_stats,
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CSRs.tohost -> reg_tohost,
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CSRs.fromhost -> reg_fromhost)
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for (i <- 0 until reg_uarch_counters.size)
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read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
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io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
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io.fcsr_rm := reg_frm
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@ -326,26 +328,23 @@ class CSRFile extends CoreModule
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reg_mstatus.msip := new_mstatus.msip
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reg_mstatus.stie := new_mstatus.stie
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reg_mstatus.ie := new_mstatus.ie
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reg_mstatus.ie1 := new_mstatus.ie1
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reg_mstatus.ie2 := new_mstatus.ie2
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when (new_mstatus.mprv != PRV_H) { reg_mstatus.mprv := new_mstatus.mprv }
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when (new_mstatus.prv != PRV_H) { reg_mstatus.prv := new_mstatus.prv }
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when (new_mstatus.prv1 != PRV_H) { reg_mstatus.prv1 := new_mstatus.prv1 }
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when (new_mstatus.prv2 != PRV_H) { reg_mstatus.prv2 := new_mstatus.prv2 }
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val supportedModes = Vec((PRV_M :: PRV_U :: (if (params(UseVM)) List(PRV_S) else Nil)).map(UInt(_)))
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if (supportedModes.size > 1) {
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when (supportedModes contains new_mstatus.mprv) { reg_mstatus.mprv := new_mstatus.mprv }
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when (supportedModes contains new_mstatus.prv) { reg_mstatus.prv := new_mstatus.prv }
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when (supportedModes contains new_mstatus.prv1) { reg_mstatus.prv1 := new_mstatus.prv1 }
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reg_mstatus.ie1 := new_mstatus.ie1
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if (supportedModes.size > 2) {
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when (supportedModes contains new_mstatus.prv2) { reg_mstatus.prv2 := new_mstatus.prv2 }
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reg_mstatus.ie2 := new_mstatus.ie2
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}
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}
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if (params(UseVM)) when (new_mstatus.vm === 0 || new_mstatus.vm === 5) { reg_mstatus.vm := new_mstatus.vm }
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if (!params(BuildFPU).isEmpty) reg_mstatus.fs := new_mstatus.fs
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if (params(UseVM) || !params(BuildFPU).isEmpty) reg_mstatus.fs := new_mstatus.fs
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if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_mstatus.xs
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}
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when (decoded_addr(CSRs.sstatus)) {
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val new_sstatus = new SStatus().fromBits(wdata)
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reg_mstatus.ssip := new_sstatus.sip
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reg_mstatus.stie := new_sstatus.tie
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reg_mstatus.ie := new_sstatus.ie
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reg_mstatus.ie1 := new_sstatus.pie
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reg_mstatus.prv1 := Mux(new_sstatus.ps, PRV_S, PRV_U)
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if (!params(BuildFPU).isEmpty) reg_mstatus.fs := new_sstatus.fs
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if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_sstatus.xs
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}
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when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
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when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
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when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
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@ -353,7 +352,6 @@ class CSRFile extends CoreModule
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when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
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when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
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when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata }
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when (decoded_addr(CSRs.sepc)) { reg_sepc := wdata(vaddrBits,0).toSInt }
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when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata(vaddrBits-1,0).toSInt }
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when (decoded_addr(CSRs.scycle)) { reg_time := wdata.toUInt }
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when (decoded_addr(CSRs.stime)) { reg_time := wdata.toUInt }
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@ -361,9 +359,22 @@ class CSRFile extends CoreModule
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when (decoded_addr(CSRs.stimecmp)) { reg_stimecmp := wdata(31,0).toUInt; r_irq_timer := Bool(false) }
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when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
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when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
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when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
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when (decoded_addr(CSRs.sptbr)) { reg_sptbr := Cat(wdata(paddrBits-1, pgIdxBits), Bits(0, pgIdxBits)).toUInt }
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when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
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if (params(UseVM)) {
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when (decoded_addr(CSRs.sstatus)) {
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val new_sstatus = new SStatus().fromBits(wdata)
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reg_mstatus.ssip := new_sstatus.sip
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reg_mstatus.stie := new_sstatus.tie
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reg_mstatus.ie := new_sstatus.ie
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reg_mstatus.ie1 := new_sstatus.pie
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reg_mstatus.prv1 := Mux(new_sstatus.ps, PRV_S, PRV_U)
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if (!params(BuildFPU).isEmpty) reg_mstatus.fs := new_sstatus.fs
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if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_sstatus.xs
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}
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when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
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when (decoded_addr(CSRs.sptbr)) { reg_sptbr := Cat(wdata(paddrBits-1, pgIdxBits), Bits(0, pgIdxBits)).toUInt }
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when (decoded_addr(CSRs.sepc)) { reg_sepc := wdata(vaddrBits,0).toSInt }
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}
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}
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io.host.ipi_rep.ready := true
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@ -377,9 +388,9 @@ class CSRFile extends CoreModule
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reg_mstatus.ie := false
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reg_mstatus.prv := PRV_M
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reg_mstatus.ie1 := false
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reg_mstatus.prv1 := PRV_S
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reg_mstatus.prv1 := PRV_U /* hard-wired to 0 when missing user mode */
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reg_mstatus.ie2 := false
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reg_mstatus.prv2 := PRV_S
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reg_mstatus.prv2 := PRV_U /* hard-wired to 0 when missing supervisor mode */
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reg_mstatus.mprv := PRV_M
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reg_mstatus.zero2 := 0
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reg_mstatus.vm := 0
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