Use UInt instead of Vec[Bool]
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57930e8a26
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@ -133,7 +133,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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val invalidate = Bool(INPUT)
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}
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val idxValid = Reg(Vec(Bool(), entries))
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val idxValid = Reg(init=UInt(0, entries))
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val idxs = Mem(UInt(width=matchBits), entries)
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val idxPages = Mem(UInt(width=log2Up(nPages)), entries)
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val tgts = Mem(UInt(width=matchBits), entries)
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@ -152,12 +152,11 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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val p = page(addr)
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Vec(pages.map(_ === p)).toBits & pageValid
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}
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private def tagMatch(addr: UInt, pgMatch: UInt): Vec[Bool] = {
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private def tagMatch(addr: UInt, pgMatch: UInt) = {
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val idx = addr(matchBits-1,0)
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val idxMatch = idxs.map(_ === idx).toBits
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
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Vec(for (i <- 0 until entries)
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yield idxValid(i) && idxMatch(i) && idxPageMatch(i))
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idxValid & idxMatch & idxPageMatch
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}
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val r_btb_update = Pipe(io.btb_update)
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@ -199,14 +198,14 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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val nextRepl = Counter(!updateHit, entries)._1
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val waddr =
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if (updates_out_of_order) Mux(updateHits.reduce(_||_), OHToUInt(updateHits), nextRepl)
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if (updates_out_of_order) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
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else Mux(updateHit, r_btb_update.bits.prediction.bits.entry, nextRepl)
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// invalidate entries if we stomp on pages they depend upon
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for (i <- 0 until idxValid.size)
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when ((pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR) { idxValid(i) := false }
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val invalidateMask = Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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val validateMask = UIntToOH(waddr)
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idxValid := (idxValid & ~invalidateMask) | validateMask
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idxValid(waddr) := Bool(true)
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idxs(waddr) := r_btb_update.bits.pc
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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@ -239,7 +238,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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pageValid := 0
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}
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io.resp.valid := hits.reduce(_||_)
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io.resp.valid := hits.orR
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io.resp.bits.taken := io.resp.valid
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.bits.entry := OHToUInt(hits)
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