Only instantiate div/sqrt unit if requested
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@ -434,10 +434,8 @@ class FPU extends Module
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fpmu.io.in.bits := req
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fpmu.io.lt := fpiu.io.out.bits.lt
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val divSqrt = Module(new hardfloat.divSqrtRecodedFloat64)
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val divSqrt_inReady = Mux(divSqrt.io.sqrtOp, divSqrt.io.inReady_sqrt, divSqrt.io.inReady_div)
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val divSqrt_outValid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt
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val divSqrt_wen = Reg(next=Bool(false))
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val divSqrt_inReady = Wire(init=Bool(false))
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val divSqrt_waddr = Reg(Bits())
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val divSqrt_wdata = Wire(Bits())
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val divSqrt_flags = Wire(Bits())
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@ -512,7 +510,9 @@ class FPU extends Module
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val divSqrt_flags_double = Reg(Bits())
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val divSqrt_wdata_double = Reg(Bits())
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def upconvert(x: UInt) = hardfloat.recodedFloatNToRecodedFloatM(x, Bits(0), 23, 9, 52, 12)._1
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val divSqrt = Module(new hardfloat.divSqrtRecodedFloat64)
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divSqrt_inReady := Mux(divSqrt.io.sqrtOp, divSqrt.io.inReady_sqrt, divSqrt.io.inReady_div)
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val divSqrt_outValid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt
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val divSqrt_wb_hazard = wen.orR
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divSqrt.io.inValid := mem_reg_valid && !divSqrt_wb_hazard && !divSqrt_in_flight && !io.killm && (mem_ctrl.div || mem_ctrl.sqrt)
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divSqrt.io.sqrtOp := mem_ctrl.sqrt
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