52d6b0b1a55249bd12ba2fb747c4b78e4cdfa121
Rejigger muxes; share XOR gates between ADD/SUB, XOR, and BEQ.
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%