riscv/rocket-chip
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Andrew Waterman 52d6b0b1a5 Improve ALU QoR 
Rejigger muxes; share XOR gates between ADD/SUB, XOR, and BEQ.
2016-01-20 17:42:31 -08:00
rocket
Improve ALU QoR
2016-01-20 17:42:31 -08:00
Description
Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
13 MiB
Languages
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%