riscv/rocket-chip
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Remove hard-coded XLEN values from D$

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This commit is contained in:
Andrew Waterman 2016-03-24 14:52:12 -07:00
parent 7ae44d4905
commit 8d1ba4d1ec
1 changed files with 6 additions and 6 deletions
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12
rocket/src/main/scala/nbdcache.scala
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@ -153,7 +153,7 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
def wordFromBeat(addr: UInt, dat: UInt) = {
val offset = addr(beatOffBits - 1, wordOffBits)
val shift = Cat(offset, UInt(0, wordOffBits + 3))
val shift = Cat(offset, UInt(0, wordOffBits + log2Up(wordBytes)))
(dat >> shift)(wordBits - 1, 0)
}
@ -161,8 +161,8 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val req_cmd_sc = req.cmd === M_XSC
val grant_word = Reg(UInt(width = wordBits))
val storegen = new StoreGen(req.typ, req.addr, req.data, wordBits/8)
val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc, wordBits/8)
val storegen = new StoreGen(req.typ, req.addr, req.data, wordBytes)
val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc, wordBytes)
val beat_offset = req.addr(beatOffBits - 1, wordOffBits)
val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
@ -814,7 +814,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
s2_req.cmd := s1_req.cmd
}
val misaligned = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBits/8).misaligned
val misaligned = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes).misaligned
io.cpu.xcpt.ma.ld := s1_read && misaligned
io.cpu.xcpt.ma.st := s1_write && misaligned
io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
@ -906,7 +906,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val s2_data_decoded = (0 until rowWords).map(i => code.decode(s2_data_muxed(encDataBits*(i+1)-1,encDataBits*i)))
val s2_data_corrected = Vec(s2_data_decoded.map(_.corrected)).toBits
val s2_data_uncorrected = Vec(s2_data_decoded.map(_.uncorrected)).toBits
val s2_word_idx = if(doNarrowRead) UInt(0) else s2_req.addr(log2Up(rowWords*coreDataBytes)-1,3)
val s2_word_idx = if(doNarrowRead) UInt(0) else s2_req.addr(log2Up(rowWords*coreDataBytes)-1,log2Up(wordBytes))
val s2_data_correctable = Vec(s2_data_decoded.map(_.correctable)).toBits()(s2_word_idx)
// store/amo hits
@ -1013,7 +1013,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
// load data subword mux/sign extension
val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(coreDataBits)))
val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc, wordBits/8)
val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc, wordBytes)
amoalu.io.addr := s2_req.addr
amoalu.io.cmd := s2_req.cmd