Remove four integer/FP converters
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31d537c405
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7bf503a275
@ -235,9 +235,7 @@ class FPToInt extends Module
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when (io.in.valid) {
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in := io.in.bits
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when (io.in.bits.single && !io.in.bits.ldst && io.in.bits.cmd != FCMD_MV_XF &&
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// need to also check toint because CVT_IF and SQRT overlap
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!(io.in.bits.cmd === FCMD_CVT_IF && io.in.bits.toint)) {
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when (io.in.bits.single && !io.in.bits.ldst && io.in.bits.cmd != FCMD_MV_XF) {
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in.in1 := in1_upconvert
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in.in2 := in2_upconvert
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}
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@ -258,23 +256,14 @@ class FPToInt extends Module
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val dcmp_out = (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR
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val dcmp_exc = dcmp.io.exceptionFlags
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val s2l = Module(new hardfloat.RecFNToIN(8, 24, 64))
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val s2w = Module(new hardfloat.RecFNToIN(8, 24, 32))
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s2l.io.in := in.in1
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s2l.io.roundingMode := in.rm
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s2l.io.signedOut := in.typ(0) ^ 1
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s2w.io.in := in.in1
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s2w.io.roundingMode := in.rm
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s2w.io.signedOut := in.typ(0) ^ 1
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val d2l = Module(new hardfloat.RecFNToIN(11, 53, 64))
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val d2w = Module(new hardfloat.RecFNToIN(11, 53, 32))
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d2l.io.in := in.in1
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d2l.io.roundingMode := in.rm
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d2l.io.signedOut := in.typ(0) ^ 1
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d2l.io.signedOut := ~in.typ(0)
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d2w.io.in := in.in1
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d2w.io.roundingMode := in.rm
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d2w.io.signedOut := in.typ(0) ^ 1
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d2w.io.signedOut := ~in.typ(0)
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io.out.bits.toint := Mux(in.rm(0), classify_out, unrec_out)
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io.out.bits.store := unrec_out
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@ -285,15 +274,9 @@ class FPToInt extends Module
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io.out.bits.exc := dcmp_exc
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}
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when (in.cmd === FCMD_CVT_IF) {
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when (in.single) {
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io.out.bits.toint := Mux(in.typ(1), s2l.io.out, s2w.io.out.toSInt).toUInt
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val sflags = Mux(in.typ(1), s2l.io.intExceptionFlags, s2w.io.intExceptionFlags)
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io.out.bits.exc := Cat(sflags(2, 1).orR, UInt(0, 3), sflags(0))
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} .otherwise {
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io.out.bits.toint := Mux(in.typ(1), d2l.io.out, d2w.io.out.toSInt).toUInt
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val dflags = Mux(in.typ(1), d2l.io.intExceptionFlags, d2w.io.intExceptionFlags)
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io.out.bits.exc := Cat(dflags(2, 1).orR, UInt(0, 3), dflags(0))
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}
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io.out.bits.toint := Mux(in.typ(1), d2l.io.out.toSInt, d2w.io.out.toSInt).toUInt
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val dflags = Mux(in.typ(1), d2l.io.intExceptionFlags, d2w.io.intExceptionFlags)
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io.out.bits.exc := Cat(dflags(2, 1).orR, UInt(0, 3), dflags(0))
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}
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io.out.valid := valid
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@ -317,31 +300,26 @@ class IntToFP(val latency: Int) extends Module
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mux.data := Cat(SInt(-1, 32), hardfloat.recFNFromFN(8, 24, in.bits.in1))
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}
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val longValue =
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Mux(in.bits.typ(1), in.bits.in1.toSInt,
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Mux(in.bits.typ(0), in.bits.in1(31,0).zext, in.bits.in1(31,0).toSInt))
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val l2s = Module(new hardfloat.INToRecFN(64, 8, 24))
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val w2s = Module(new hardfloat.INToRecFN(32, 8, 24))
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l2s.io.signedIn := in.bits.typ(0) ^ 1
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l2s.io.in := in.bits.in1
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l2s.io.signedIn := ~in.bits.typ(0)
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l2s.io.in := longValue
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l2s.io.roundingMode := in.bits.rm
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w2s.io.signedIn := in.bits.typ(0) ^ 1
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w2s.io.in := in.bits.in1
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w2s.io.roundingMode := in.bits.rm
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val l2d = Module(new hardfloat.INToRecFN(64, 11, 53))
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val w2d = Module(new hardfloat.INToRecFN(32, 11, 53))
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l2d.io.signedIn := in.bits.typ(0) ^ 1
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l2d.io.in := in.bits.in1
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l2d.io.signedIn := ~in.bits.typ(0)
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l2d.io.in := longValue
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l2d.io.roundingMode := in.bits.rm
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w2d.io.signedIn := in.bits.typ(0) ^ 1
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w2d.io.in := in.bits.in1
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w2d.io.roundingMode := in.bits.rm
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when (in.bits.cmd === FCMD_CVT_FI) {
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when (in.bits.single) {
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mux.data := Cat(SInt(-1, 32), Mux(in.bits.typ(1), l2s.io.out, w2s.io.out))
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mux.exc := Mux(in.bits.typ(1), l2s.io.exceptionFlags, w2s.io.exceptionFlags)
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mux.data := Cat(SInt(-1, 32), l2s.io.out)
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mux.exc := l2s.io.exceptionFlags
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}.otherwise {
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mux.data := Mux(in.bits.typ(1), l2d.io.out, w2d.io.out)
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mux.exc := Mux(in.bits.typ(1), l2d.io.exceptionFlags, w2d.io.exceptionFlags)
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mux.data := l2d.io.out
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mux.exc := l2d.io.exceptionFlags
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}
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}
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