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Avoid spurious D$ assertion failures

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For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
This commit is contained in:
Andrew Waterman
2015-05-19 02:56:20 -07:00
parent f460cb6c54
commit 6a9390c50e
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/nbdcache.scala
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@@ -670,8 +670,8 @@ class HellaCache extends L1HellaCacheModule {
io.cpu.xcpt.ma.ld := s1_read && misaligned
io.cpu.xcpt.ma.st := s1_write && misaligned
io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st
io.cpu.xcpt.pf.ld := !s1_req.phys && s1_read && dtlb.io.resp.xcpt_ld
io.cpu.xcpt.pf.st := !s1_req.phys && s1_write && dtlb.io.resp.xcpt_st
assert (!(Reg(next=
(io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) &&