New virtual memory implementation (Sv39)
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@ -27,7 +27,8 @@ abstract trait CoreParameters extends UsesParameters {
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val pgIdxBits = params(PgIdxBits)
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val ppnBits = params(PPNBits)
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val vpnBits = params(VPNBits)
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val permBits = params(PermBits)
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val pgLevels = params(PgLevels)
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val pgLevelBits = params(PgLevelBits)
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val asIdBits = params(ASIdBits)
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val retireWidth = params(RetireWidth)
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@ -8,7 +8,9 @@ import Util._
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class PTWReq extends CoreBundle {
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val addr = UInt(width = vpnBits)
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val perm = Bits(width = permBits)
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val prv = Bits(width = 2)
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val store = Bool()
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val fetch = Bool()
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}
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class PTWResp extends CoreBundle {
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@ -34,10 +36,20 @@ class PTE extends CoreBundle {
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val reserved = Bits(width = 2)
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val d = Bool()
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val r = Bool()
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val perm = Bits(width = 6)
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val g = Bool()
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val t = Bool()
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val v = Bool()
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val perm = Bits(width = 2)
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val typ = Bits(width = 3)
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def table(dummy: Int = 0) = typ === 1
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def leaf(dummy: Int = 0) = typ >= 2
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def ur(dummy: Int = 0) = typ === 2 || typ >= 4
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def uw(dummy: Int = 0) = ur() && perm(0)
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def ux(dummy: Int = 0) = ur() && perm(1)
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def sr(dummy: Int = 0) = typ >= 3
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def sw(dummy: Int = 0) = Mux(typ >= 4, typ(0), typ === 3 && perm(0))
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def sx(dummy: Int = 0) = Mux(typ >= 4, typ(1), typ === 3 && perm(1))
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def access_ok(prv: Bits, store: Bool, fetch: Bool) =
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Mux(prv(0), Mux(fetch, sx(), Mux(store, sw(), sr())), Mux(fetch, ux(), Mux(store, uw(), ur())))
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}
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class PTW(n: Int) extends CoreModule
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@ -48,19 +60,15 @@ class PTW(n: Int) extends CoreModule
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val dpath = new DatapathPTWIO
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}
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val levels = 3
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val bitsPerLevel = vpnBits/levels
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require(vpnBits == levels * bitsPerLevel)
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val s_ready :: s_req :: s_wait :: s_set_dirty :: s_wait_dirty :: s_done :: s_error :: Nil = Enum(UInt(), 7)
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val state = Reg(init=s_ready)
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val count = Reg(UInt(width = log2Up(levels)))
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val count = Reg(UInt(width = log2Up(pgLevels)))
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val r_req = Reg(new PTWReq)
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val r_req_dest = Reg(Bits())
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val r_pte = Reg(new PTE)
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val vpn_idx = Vec((0 until levels).map(i => (r_req.addr >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count)
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val vpn_idx = Vec((0 until pgLevels).map(i => (r_req.addr >> (pgLevels-i-1)*pgLevelBits)(pgLevelBits-1,0)))(count)
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val arb = Module(new RRArbiter(new PTWReq, n))
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arb.io.in <> io.requestor.map(_.req)
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@ -76,19 +84,19 @@ class PTW(n: Int) extends CoreModule
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}
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val (pte_cache_hit, pte_cache_data) = {
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val size = log2Up(levels * 2)
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val size = log2Up(pgLevels * 2)
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val plru = new PseudoLRU(size)
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val valid = Reg(init = Bits(0, size))
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val tags = Mem(UInt(width = paddrBits), size)
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val data = Mem(UInt(width = paddrBits - pgIdxBits), size)
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val data = Mem(UInt(width = ppnBits), size)
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val hits = Vec(tags.map(_ === pte_addr)).toBits & valid
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val hit = hits.orR
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when (io.mem.resp.valid && io.mem.resp.bits.data(1,0).andR && !hit) {
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when (io.mem.resp.valid && pte.table() && !hit) {
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val r = Mux(valid.andR, plru.replace, PriorityEncoder(~valid))
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valid(r) := true
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tags(r) := pte_addr
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data(r) := io.mem.resp.bits.data(paddrBits-1,pgIdxBits)
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data(r) := pte.ppn
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}
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when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
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when (io.dpath.invalidate) { valid := 0 }
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@ -96,12 +104,16 @@ class PTW(n: Int) extends CoreModule
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(hit, Mux1H(hits, data))
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}
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val perm_ok = (pte.perm & r_req.perm).orR
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val is_store = r_req.perm(1) || r_req.perm(4)
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val set_dirty_bit = perm_ok && !pte.t && (!pte.r || (is_store && !pte.d))
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val perm_ok = pte.access_ok(r_req.prv, r_req.store, r_req.fetch)
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val set_dirty_bit = perm_ok && (!pte.r || (r_req.store && !pte.d))
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when (io.mem.resp.valid && state === s_wait && !set_dirty_bit) {
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r_pte := pte
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}
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val pte_wdata = new PTE
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pte_wdata := new PTE().fromBits(0)
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pte_wdata.r := true
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pte_wdata.d := r_req.store
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io.mem.req.valid := state === s_req || state === s_set_dirty
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io.mem.req.bits.phys := Bool(true)
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@ -109,13 +121,13 @@ class PTW(n: Int) extends CoreModule
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.addr := pte_addr
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io.mem.req.bits.kill := Bool(false)
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io.mem.req.bits.data := UInt(1<<9) | Mux(is_store, UInt(1<<10), UInt(0))
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io.mem.req.bits.data := pte_wdata.toBits
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val resp_err = state === s_error
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val resp_val = state === s_done || resp_err
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val r_resp_ppn = io.mem.req.bits.addr >> UInt(pgIdxBits)
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val resp_ppn = Vec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req.addr(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count)
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val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count)
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for (i <- 0 until io.requestor.size) {
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val me = r_req_dest === UInt(i)
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@ -136,7 +148,7 @@ class PTW(n: Int) extends CoreModule
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count := UInt(0)
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}
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is (s_req) {
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when (pte_cache_hit && count < levels-1) {
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when (pte_cache_hit && count < pgLevels-1) {
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io.mem.req.valid := false
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state := s_req
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count := count + 1
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@ -151,15 +163,12 @@ class PTW(n: Int) extends CoreModule
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}
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when (io.mem.resp.valid) {
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state := s_error
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when (pte.v) {
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when (set_dirty_bit) {
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state := s_set_dirty
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}.elsewhen (!pte.t) {
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state := s_done
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}.elsewhen (count < levels-1) {
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state := s_req
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count := count + 1
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}
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when (pte.table() && count < pgLevels-1) {
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state := s_req
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count := count + 1
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}
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when (pte.leaf()) {
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state := Mux(set_dirty_bit, s_set_dirty, s_done)
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}
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}
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}
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@ -119,7 +119,7 @@ class TLB extends TLBModule {
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val tag_hit_addr = OHToUInt(tag_cam.io.hits)
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// permission bit arrays
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val valid_array = Reg(Bits()) // V bit of PTE (not equivalent to CAM tag valid bit!)
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val valid_array = Reg(Bits()) // PTE is valid (not equivalent to CAM tag valid bit!)
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val ur_array = Reg(Bits()) // user read permission
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val uw_array = Reg(Bits()) // user write permission
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val ux_array = Reg(Bits()) // user execute permission
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@ -128,16 +128,16 @@ class TLB extends TLBModule {
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val sx_array = Reg(Bits()) // supervisor execute permission
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val dirty_array = Reg(Bits()) // PTE dirty bit
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when (io.ptw.resp.valid) {
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val perm = io.ptw.resp.bits.pte.perm & ~io.ptw.resp.bits.error.toSInt
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tag_ram(r_refill_waddr) := io.ptw.resp.bits.pte.ppn
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val pte = io.ptw.resp.bits.pte
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tag_ram(r_refill_waddr) := pte.ppn
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valid_array := valid_array.bitSet(r_refill_waddr, !io.ptw.resp.bits.error)
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ur_array := ur_array.bitSet(r_refill_waddr, perm(0) || perm(2))
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uw_array := uw_array.bitSet(r_refill_waddr, perm(1))
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ux_array := ux_array.bitSet(r_refill_waddr, perm(2))
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sr_array := sr_array.bitSet(r_refill_waddr, perm(3) || perm(5))
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sw_array := sw_array.bitSet(r_refill_waddr, perm(4))
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sx_array := sx_array.bitSet(r_refill_waddr, perm(5))
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dirty_array := dirty_array.bitSet(r_refill_waddr, io.ptw.resp.bits.pte.d)
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ur_array(r_refill_waddr) := pte.ur() && !io.ptw.resp.bits.error
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uw_array(r_refill_waddr) := pte.uw() && !io.ptw.resp.bits.error
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ux_array(r_refill_waddr) := pte.ux() && !io.ptw.resp.bits.error
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sr_array(r_refill_waddr) := pte.sr() && !io.ptw.resp.bits.error
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sw_array(r_refill_waddr) := pte.sw() && !io.ptw.resp.bits.error
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sx_array(r_refill_waddr) := pte.sx() && !io.ptw.resp.bits.error
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dirty_array(r_refill_waddr) := pte.d
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}
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// high if there are any unused (invalid) entries in the TLB
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@ -150,7 +150,6 @@ class TLB extends TLBModule {
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val priv_s = priv === PRV_S
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val priv_uses_vm = priv <= PRV_S
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val req_xwr = Cat(!r_req.store, r_req.store, !(r_req.instruction || r_req.store))
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val req_perm = Cat(req_xwr & priv_s.toSInt, req_xwr & ~priv_s.toSInt)
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val r_array = Mux(priv_s, sr_array, ur_array)
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val w_array = Mux(priv_s, sw_array, uw_array)
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@ -183,7 +182,9 @@ class TLB extends TLBModule {
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io.ptw.req.valid := state === s_request
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io.ptw.req.bits.addr := r_refill_tag
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io.ptw.req.bits.perm := req_perm
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io.ptw.req.bits.prv := io.ptw.status.prv
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io.ptw.req.bits.store := r_req.store
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io.ptw.req.bits.fetch := r_req.instruction
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when (io.req.fire() && tlb_miss) {
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state := s_request
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