Chisel3 has different Vec semantics
Vec(a, b) := c doesn't modify a and b in chisel3.
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@ -55,9 +55,10 @@ class IntCtrlSigs extends Bundle {
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def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
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val decoder = DecodeLogic(inst, XDecode.decode_default, table)
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Vec(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2, sel_alu1,
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sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type,
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rfs1, rfs2, rfs3, wfd, div, wxd, csr, fence_i, fence, amo) := decoder
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val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2,
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sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type,
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rfs1, rfs2, rfs3, wfd, div, wxd, csr, fence_i, fence, amo)
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sigs zip decoder map {case(s,d) => s := d}
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this
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}
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}
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