Make ALU generic for zscale
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5294e94794
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@ -43,17 +43,15 @@ object ALU
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}
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import ALU._
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class ALUIO(implicit p: Parameters) extends CoreBundle()(p) {
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val dw = Bits(INPUT, SZ_DW)
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val fn = Bits(INPUT, SZ_ALU_FN)
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val in2 = UInt(INPUT, xLen)
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val in1 = UInt(INPUT, xLen)
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val out = UInt(OUTPUT, xLen)
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val adder_out = UInt(OUTPUT, xLen)
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}
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class ALU(implicit p: Parameters) extends Module {
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val io = new ALUIO
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class ALU(xLen: Int) extends Module {
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val io = new Bundle {
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val dw = Bits(INPUT, SZ_DW)
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val fn = Bits(INPUT, SZ_ALU_FN)
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val in2 = UInt(INPUT, xLen)
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val in1 = UInt(INPUT, xLen)
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val out = UInt(OUTPUT, xLen)
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val adder_out = UInt(OUTPUT, xLen)
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}
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// ADD, SUB
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val sum = io.in1 + Mux(isSub(io.fn), -io.in2, io.in2)
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@ -61,19 +59,26 @@ class ALU(implicit p: Parameters) extends Module {
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// SLT, SLTU
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val cmp = cmpInverted(io.fn) ^
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Mux(cmpEq(io.fn), sum === UInt(0),
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Mux(io.in1(63) === io.in2(63), sum(63),
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Mux(cmpUnsigned(io.fn), io.in2(63), io.in1(63))))
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Mux(io.in1(xLen-1) === io.in2(xLen-1), sum(xLen-1),
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Mux(cmpUnsigned(io.fn), io.in2(xLen-1), io.in1(xLen-1))))
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// SLL, SRL, SRA
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val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0)).toUInt
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val shin_hi_32 = Mux(isSub(io.fn), Fill(32, io.in1(31)), UInt(0,32))
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val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
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val shin_r = Cat(shin_hi, io.in1(31,0))
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val full_shamt = io.in2(log2Up(xLen)-1,0)
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val (shamt, shin_r) =
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if (xLen == 32) (full_shamt, io.in1)
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else {
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require(xLen == 64)
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val shin_hi_32 = Fill(32, isSub(io.fn) && io.in1(31))
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val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
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val shamt = Cat(full_shamt(5) & (io.dw === DW_64), full_shamt(4,0))
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(shamt, Cat(shin_hi, io.in1(31,0)))
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}
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val shin = Mux(io.fn === FN_SR || io.fn === FN_SRA, shin_r, Reverse(shin_r))
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val shout_r = (Cat(isSub(io.fn) & shin(63), shin).toSInt >> shamt)(63,0)
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val shout_r = (Cat(isSub(io.fn) & shin(xLen-1), shin).toSInt >> shamt)(xLen-1,0)
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val shout_l = Reverse(shout_r)
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val out64 =
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val out =
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Mux(io.fn === FN_ADD || io.fn === FN_SUB, sum,
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Mux(io.fn === FN_SR || io.fn === FN_SRA, shout_r,
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Mux(io.fn === FN_SL, shout_l,
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@ -82,7 +87,10 @@ class ALU(implicit p: Parameters) extends Module {
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Mux(io.fn === FN_XOR, io.in1 ^ io.in2,
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/* all comparisons */ cmp))))))
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val out_hi = Mux(io.dw === DW_64, out64(63,32), Fill(32, out64(31)))
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io.out := Cat(out_hi, out64(31,0)).toUInt
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io.adder_out := sum
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io.out := out
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if (xLen > 32) {
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require(xLen == 64)
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when (io.dw === DW_32) { io.out := Cat(Fill(32, out(31)), out(31,0)) }
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}
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}
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@ -239,7 +239,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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A2_IMM -> ex_imm,
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A2_FOUR -> SInt(4)))
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val alu = Module(new ALU)
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val alu = Module(new ALU(xLen))
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alu.io.dw := ex_ctrl.alu_dw
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alu.io.fn := ex_ctrl.alu_fn
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alu.io.in2 := ex_op2.toUInt
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