Add Wire() wrap
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@ -56,7 +56,7 @@ class BHTResp extends Bundle with BTBParameters {
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class BHT(nbht: Int) {
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val nbhtbits = log2Up(nbht)
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def get(addr: UInt, update: Bool): BHTResp = {
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val res = new BHTResp
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val res = Wire(new BHTResp)
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val index = addr(nbhtbits+1,2) ^ history
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res.value := table(index)
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res.history := history
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@ -178,7 +178,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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val useUpdatePageHit = updatePageHit.orR
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val doIdxPageRepl = !useUpdatePageHit
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val idxPageRepl = UInt()
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val idxPageRepl = Wire(UInt())
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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@ -134,7 +134,7 @@ class CSRFile extends CoreModule
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io.interrupt_cause := 0
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io.interrupt := io.interrupt_cause(xLen-1)
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val some_interrupt_pending = Bool(); some_interrupt_pending := false
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val some_interrupt_pending = Wire(init=Bool(false))
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def checkInterrupt(max_priv: UInt, cond: Bool, num: Int) = {
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when (cond && (reg_mstatus.prv < max_priv || reg_mstatus.prv === max_priv && reg_mstatus.ie)) {
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io.interrupt_cause := UInt((BigInt(1) << (xLen-1)) + num)
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@ -216,20 +216,17 @@ class CSRFile extends CoreModule
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CSRs.mfromhost -> reg_fromhost)
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if (params(UseVM)) {
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val read_sstatus = new SStatus
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read_sstatus := new SStatus().fromBits(read_mstatus) // sstatus mostly overlaps mstatus
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val read_sstatus = Wire(init=new SStatus().fromBits(read_mstatus))
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read_sstatus.zero1 := 0
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read_sstatus.zero2 := 0
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read_sstatus.zero3 := 0
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read_sstatus.zero4 := 0
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val read_sip = new MIP
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read_sip := new MIP().fromBits(0)
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val read_sip = Wire(init=new MIP().fromBits(0))
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read_sip.ssip := reg_mip.ssip
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read_sip.stip := reg_mip.stip
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val read_sie = new MIP
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read_sie := new MIP().fromBits(0)
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val read_sie = Wire(init=new MIP().fromBits(0))
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read_sie.ssip := reg_mie.ssip
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read_sie.stip := reg_mie.stip
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@ -359,7 +359,7 @@ class Control extends CoreModule
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if (!params(BuildFPU).isEmpty && params(FDivSqrt)) decode_table ++= FDivSqrtDecode.table
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if (!params(BuildRoCC).isEmpty) decode_table ++= RoCCDecode.table
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val id_ctrl = new IntCtrlSigs().decode(io.dpath.inst, decode_table)
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val id_ctrl = Wire(new IntCtrlSigs()).decode(io.dpath.inst, decode_table)
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val ex_ctrl = Reg(new IntCtrlSigs)
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val mem_ctrl = Reg(new IntCtrlSigs)
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val wb_ctrl = Reg(new IntCtrlSigs)
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@ -389,21 +389,21 @@ class Control extends CoreModule
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val wb_reg_cause = Reg(UInt())
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val wb_reg_rocc_pending = Reg(init=Bool(false))
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val take_pc_wb = Bool()
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val take_pc_wb = Wire(Bool())
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val mem_misprediction = io.dpath.mem_misprediction && mem_reg_valid && (mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal)
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val want_take_pc_mem = mem_reg_valid && (mem_misprediction || mem_reg_flush_pipe)
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val take_pc_mem = want_take_pc_mem && !io.dpath.mem_npc_misaligned
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val take_pc_mem_wb = take_pc_wb || take_pc_mem
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val take_pc = take_pc_mem_wb
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val ctrl_killd = Bool()
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val ctrl_killx = Bool()
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val ctrl_killm = Bool()
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val ctrl_killd = Wire(Bool())
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val ctrl_killx = Wire(Bool())
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val ctrl_killm = Wire(Bool())
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val id_raddr3 = io.dpath.inst(31,27)
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val id_raddr2 = io.dpath.inst(24,20)
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val id_raddr1 = io.dpath.inst(19,15)
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val id_waddr = io.dpath.inst(11,7)
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val id_load_use = Bool()
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val id_load_use = Wire(Bool())
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val id_reg_fence = Reg(init=Bool(false))
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val id_csr_en = id_ctrl.csr != CSR.N
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@ -38,7 +38,7 @@ class Datapath extends CoreModule
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val wb_reg_pc = Reg(UInt())
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val wb_reg_inst = Reg(Bits())
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val wb_reg_wdata = Reg(Bits())
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val wb_wdata = Bits()
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val wb_wdata = Wire(Bits())
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val wb_reg_rs2 = Reg(Bits())
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// instruction decode stage
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@ -51,7 +51,7 @@ class Datapath extends CoreModule
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private var canRead = true
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def read(addr: UInt) = {
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require(canRead)
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reads += addr -> UInt()
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reads += addr -> Wire(UInt())
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reads.last._2 := rf(~addr)
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reads.last._2
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}
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@ -109,7 +109,7 @@ class Datapath extends CoreModule
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}
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}
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val bypass = Vec.fill(NBYP)(Bits())
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val bypass = Wire(Vec(Bits(), NBYP))
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bypass(BYP_0) := Bits(0)
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bypass(BYP_EX) := mem_reg_wdata
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bypass(BYP_MEM) := wb_reg_wdata
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@ -198,7 +198,7 @@ class Datapath extends CoreModule
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val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
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val dmem_resp_replay = io.dmem.resp.bits.replay && io.dmem.resp.bits.has_data
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val ll_wdata = Bits()
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val ll_wdata = Wire(Bits())
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div.io.resp.ready := io.ctrl.ll_ready
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ll_wdata := div.io.resp.bits.data
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io.ctrl.ll_waddr := div.io.resp.bits.tag
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@ -248,7 +248,7 @@ class IntToFP(val latency: Int) extends Module
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val in = Pipe(io.in)
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val mux = new FPResult
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val mux = Wire(new FPResult)
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mux.exc := Bits(0)
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mux.data := hardfloat.floatNToRecodedFloatN(in.bits.in1, 52, 12)
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when (in.bits.single) {
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@ -299,7 +299,7 @@ class FPToFP(val latency: Int) extends Module
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val isMax = in.bits.rm(0)
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val isLHS = isnan2 || isMax != io.lt && !isnan1
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val mux = new FPResult
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val mux = Wire(new FPResult)
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mux.exc := minmax_exc
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mux.data := in.bits.in2
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@ -347,7 +347,7 @@ class FPUFMAPipe(val latency: Int, sigWidth: Int, expWidth: Int) extends Module
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fma.io.b := in.in2
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fma.io.c := in.in3
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val res = new FPResult
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val res = Wire(new FPResult)
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res.data := fma.io.out
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res.exc := fma.io.exceptionFlags
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io.out := Pipe(valid, res, latency-1)
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@ -404,7 +404,7 @@ class FPU extends Module
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val ex_rs1::ex_rs2::ex_rs3::Nil = Seq(ex_ra1, ex_ra2, ex_ra3).map(regfile(_))
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val ex_rm = Mux(ex_reg_inst(14,12) === Bits(7), io.dpath.fcsr_rm, ex_reg_inst(14,12))
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val req = new FPInput
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val req = Wire(new FPInput)
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req := ex_ctrl
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req.rm := ex_rm
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req.in1 := ex_rs1
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@ -441,8 +441,8 @@ class FPU extends Module
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val divSqrt_outValid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt
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val divSqrt_wen = Reg(next=Bool(false))
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val divSqrt_waddr = Reg(Bits())
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val divSqrt_wdata = Bits()
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val divSqrt_flags = Bits()
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val divSqrt_wdata = Wire(Bits())
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val divSqrt_flags = Wire(Bits())
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val divSqrt_in_flight = Reg(init=Bool(false))
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// writeback arbitration
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@ -158,11 +158,11 @@ class ICache extends FrontendModule
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val state = Reg(init=s_ready)
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val invalidated = Reg(Bool())
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val stall = !io.resp.ready
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val rdy = Bool()
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val rdy = Wire(Bool())
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val s2_valid = Reg(init=Bool(false))
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val s2_addr = Reg(UInt(width = paddrBits))
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val s2_any_tag_hit = Bool()
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val s2_any_tag_hit = Wire(Bool())
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val s1_valid = Reg(init=Bool(false))
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val s1_pgoff = Reg(UInt(width = pgIdxBits))
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@ -212,13 +212,13 @@ class ICache extends FrontendModule
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vb_array := Bits(0)
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invalidated := Bool(true)
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}
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val s2_disparity = Vec.fill(nWays){Bool()}
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val s2_disparity = Wire(Vec(Bool(), nWays))
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for (i <- 0 until nWays)
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when (s2_valid && s2_disparity(i)) { vb_array := vb_array.bitSet(Cat(UInt(i), s2_idx), Bool(false)) }
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val s1_tag_match = Vec.fill(nWays){Bool()}
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val s2_tag_hit = Vec.fill(nWays){Bool()}
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val s2_dout = Reg(Vec.fill(nWays){Bits()})
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val s1_tag_match = Wire(Vec(Bool(), nWays))
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val s2_tag_hit = Wire(Vec(Bool(), nWays))
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val s2_dout = Reg(Vec(Bits(), nWays))
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for (i <- 0 until nWays) {
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val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool
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@ -108,7 +108,7 @@ class L1MetaWriteReq extends
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object L1Metadata {
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def apply(tag: Bits, coh: ClientMetadata) = {
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val meta = new L1Metadata
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val meta = Wire(new L1Metadata)
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meta.tag := tag
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meta.coh := coh
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meta
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@ -303,12 +303,12 @@ class MSHRFile extends L1HellaCacheModule {
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val sdq = Mem(io.req.bits.data, sdqDepth)
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when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
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val idxMatch = Vec.fill(nMSHRs){Bool()}
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val tagList = Vec.fill(nMSHRs){Bits()}
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val idxMatch = Wire(Vec(Bool(), nMSHRs))
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val tagList = Wire(Vec(Bits(), nMSHRs))
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val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits
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val wbTagList = Vec.fill(nMSHRs){Bits()}
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val refillMux = Vec.fill(nMSHRs){new L1RefillReq}
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val wbTagList = Wire(Vec(Bits(), nMSHRs))
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val refillMux = Wire(Vec(new L1RefillReq, nMSHRs))
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val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs))
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val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
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val mem_req_arb = Module(new LockingArbiter(
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@ -548,7 +548,7 @@ class DataArray extends L1HellaCacheModule {
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for (w <- 0 until nWays by rowWords) {
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val wway_en = io.write.bits.way_en(w+rowWords-1,w)
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val rway_en = io.read.bits.way_en(w+rowWords-1,w)
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val resp = Vec.fill(rowWords){Bits(width = encRowBits)}
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val resp = Wire(Vec(Bits(width = encRowBits), rowWords))
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val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
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for (p <- 0 until resp.size) {
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val array = SeqMem(Bits(width=encRowBits), nSets*refillCycles)
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@ -610,8 +610,8 @@ class HellaCache extends L1HellaCacheModule {
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val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
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val s2_req = Reg(io.cpu.req.bits)
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val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
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val s2_recycle = Bool()
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val s2_valid_masked = Bool()
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val s2_recycle = Wire(Bool())
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val s2_valid_masked = Wire(Bool())
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val s3_valid = Reg(init=Bool(false))
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val s3_req = Reg(io.cpu.req.bits)
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@ -747,7 +747,7 @@ class HellaCache extends L1HellaCacheModule {
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}
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when (io.cpu.invalidate_lr) { lrsc_count := 0 }
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val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
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val s2_data = Wire(Vec(Bits(width=encRowBits), nWays))
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for (w <- 0 until nWays) {
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val regs = Reg(Vec.fill(rowWords){Bits(width = encDataBits)})
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val en1 = s1_clk_en && s1_tag_eq_way(w)
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@ -109,8 +109,7 @@ class PTW(n: Int) extends CoreModule
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r_pte := pte
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}
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val pte_wdata = new PTE
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pte_wdata := new PTE().fromBits(0)
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val pte_wdata = Wire(init=new PTE().fromBits(0))
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pte_wdata.r := true
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pte_wdata.d := r_req.store
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