Andrew Waterman faada5f110 Mask off LSBs of sepc/mepc/stvec ...

Therefore, they cannot generate misaligned instruction exceptions.
When a misaligned instruction exception does occur, mbadaddr
retains the misaligned PC bits, so no information is actually lost.

2015-03-25 00:20:58 -07:00

rocket

Mask off LSBs of sepc/mepc/stvec

2015-03-25 00:20:58 -07:00

S

Description

Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)

13 MiB

Languages

Scala 93.1%

C++ 2.1%

Python 2%

Makefile 1.2%

Verilog 0.8%

Other 0.7%