riscv/rocket-chip
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Mask off LSBs of sepc/mepc/stvec

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Therefore, they cannot generate misaligned instruction exceptions.
When a misaligned instruction exception does occur, mbadaddr
retains the misaligned PC bits, so no information is actually lost.
This commit is contained in:
Andrew Waterman 2015-03-25 00:20:58 -07:00
parent 543ac91cf2
commit faada5f110
1 changed files with 4 additions and 4 deletions
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8
rocket/src/main/scala/csr.scala
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@ -277,7 +277,7 @@ class CSRFile extends CoreModule
reg_mstatus.prv2 := reg_mstatus.prv1
reg_mstatus.ie2 := reg_mstatus.ie1
reg_mepc := io.pc
reg_mepc := io.pc & SInt(-coreInstBytes)
reg_mcause := io.cause
when (csr_xcpt) {
reg_mcause := Causes.illegal_instruction
@ -358,7 +358,7 @@ class CSRFile extends CoreModule
when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
when (decoded_addr(CSRs.mepc)) { reg_mepc := wdata(vaddrBits,0).toSInt }
when (decoded_addr(CSRs.mepc)) { reg_mepc := wdata(vaddrBits,0).toSInt & SInt(-coreInstBytes) }
when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata }
@ -382,8 +382,8 @@ class CSRFile extends CoreModule
}
when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
when (decoded_addr(CSRs.sptbr)) { reg_sptbr := Cat(wdata(paddrBits-1, pgIdxBits), Bits(0, pgIdxBits)).toUInt }
when (decoded_addr(CSRs.sepc)) { reg_sepc := wdata(vaddrBits,0).toSInt }
when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata(vaddrBits-1,0).toSInt }
when (decoded_addr(CSRs.sepc)) { reg_sepc := wdata(vaddrBits,0).toSInt & SInt(-coreInstBytes) }
when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata(vaddrBits-1,0).toSInt & SInt(-coreInstBytes) }
}
}