riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
1,056 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%
000e20f937
Go to file
Andrew Waterman 000e20f937 Remove MIPI; make mip.MSIP read-only 
The PRCI block outside the core will provide IPIs eventually
2016-05-02 15:18:41 -07:00
rocket Remove MIPI; make mip.MSIP read-only 2016-05-02 15:18:41 -07:00