riscv/rocket-chip
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Andrew Waterman 000e20f937 Remove MIPI; make mip.MSIP read-only 
The PRCI block outside the core will provide IPIs eventually
2016-05-02 15:18:41 -07:00
rocket
Remove MIPI; make mip.MSIP read-only
2016-05-02 15:18:41 -07:00
Description
Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
13 MiB
Languages
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%