riscv/rocket-chip
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Factor out some more hazard detection code

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This commit is contained in:
Andrew Waterman 2015-07-22 15:52:13 -07:00
parent bd785e7d19
commit b4e4ceed3d
1 changed files with 1 additions and 5 deletions
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6
rocket/src/main/scala/rocket.scala
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@ -454,11 +454,7 @@ class Rocket extends CoreModule
fp_sboard.clear(dmem_resp_replay && dmem_resp_fpu, dmem_resp_waddr)
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
id_csr_en && !io.fpu.fcsr_rdy ||
io.fpu.dec.ren1 && fp_sboard.read(id_raddr1) ||
io.fpu.dec.ren2 && fp_sboard.read(id_raddr2) ||
io.fpu.dec.ren3 && fp_sboard.read(id_raddr3) ||
io.fpu.dec.wen && fp_sboard.read(id_waddr)
id_csr_en && !io.fpu.fcsr_rdy || checkHazards(fp_hazard_targets, fp_sboard.read _)
} else Bool(false)
val ctrl_stalld =