Chisel3 compatibility changes

rocket/src/main/scala/btb.scala

@@ -4,7 +4,6 @@ package rocket
 
 import Chisel._
 import Util._
-import Node._
 import uncore._
 
 case object NBTBEntries extends Field[Int]

rocket/src/main/scala/csr.scala

@@ -5,7 +5,6 @@ package rocket
 import Chisel._
 import Util._
 import Instructions._
-import Node._
 import uncore._
 import scala.math._
 
@@ -421,7 +420,7 @@ class CSRFile extends CoreModule
         val new_sstatus = new SStatus().fromBits(wdata)
         reg_mstatus.ie := new_sstatus.ie
         reg_mstatus.ie1 := new_sstatus.pie
-        reg_mstatus.prv1 := Mux(new_sstatus.ps, PRV_S, PRV_U)
+        reg_mstatus.prv1 := Mux[UInt](new_sstatus.ps, PRV_S, PRV_U)
         reg_mstatus.mprv := new_sstatus.mprv
         reg_mstatus.fs := new_sstatus.fs // even without an FPU
         if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_sstatus.xs

rocket/src/main/scala/decode.scala

@@ -3,7 +3,6 @@
 package rocket
 
 import Chisel._
-import Node._
 
 object DecodeLogic
 {

rocket/src/main/scala/dpath_alu.scala

@@ -3,7 +3,6 @@
 package rocket
 
 import Chisel._
-import Node._
 import Instructions._
 
 object ALU

rocket/src/main/scala/instructions.scala

@@ -3,7 +3,6 @@
 package rocket
 
 import Chisel._
-import Node._
 
 /* Automatically generated by parse-opcodes */
 object Instructions {

rocket/src/main/scala/rocc.scala

@@ -3,7 +3,6 @@
 package rocket
 
 import Chisel._
-import Node._
 import uncore._
 import Util._