Stop using HTIF CSR port
The port itself is still present to keep other stuff compiling.
This commit is contained in:
Andrew Waterman
parent
0ff4fd0ccd
commit
83fa489cef
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@ -36,12 +36,11 @@ class MStatus extends Bundle {
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}
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class MIP extends Bundle {
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val host = Bool()
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val rocc = Bool()
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val mdip = Bool()
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val hdip = Bool()
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val sdip = Bool()
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val udip = Bool()
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val meip = Bool()
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val heip = Bool()
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val seip = Bool()
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val ueip = Bool()
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val mtip = Bool()
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val htip = Bool()
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val stip = Bool()
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@ -77,7 +76,7 @@ object CSR
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}
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class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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val host = new HtifIO
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val prci = new PRCICoreIO().flip
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val rw = new Bundle {
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val addr = UInt(INPUT, CSR.ADDRSZ)
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val cmd = Bits(INPUT, CSR.SZ)
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@ -123,13 +122,14 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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sup.msip := true
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sup.stip := Bool(p(UseVM))
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sup.mtip := true
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sup.meip := true
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sup.seip := Bool(p(UseVM))
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sup.rocc := usingRoCC
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sup.host := true
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val del = Wire(init=sup)
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del.msip := false
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del.mtip := false
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del.mdip := false
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del.meip := false
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(sup.toBits, del.toBits)
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}
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@ -159,8 +159,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val reg_sptbr = Reg(UInt(width = ppnBits))
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val reg_wfi = Reg(init=Bool(false))
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val reg_tohost = Reg(init=Bits(0, xLen))
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val reg_fromhost = Reg(init=Bits(0, xLen))
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val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
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val reg_fflags = Reg(UInt(width = 5))
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val reg_frm = Reg(UInt(width = 3))
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@ -169,7 +167,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val reg_cycle: UInt = if (enableCommitLog) { reg_instret } else { WideCounter(64) }
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val mip = Wire(init=reg_mip)
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mip.host := (reg_fromhost =/= 0)
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mip.rocc := io.rocc.interrupt
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val read_mip = mip.toBits & supported_interrupts
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@ -183,27 +180,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val system_insn = io.rw.cmd === CSR.I
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val cpu_ren = io.rw.cmd =/= CSR.N && !system_insn
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val host_csr_req_valid = Reg(Bool()) // don't reset
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val host_csr_req_fire = host_csr_req_valid && !cpu_ren
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val host_csr_rep_valid = Reg(Bool()) // don't reset
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val host_csr_bits = Reg(io.host.csr.req.bits)
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io.host.csr.req.ready := !host_csr_req_valid && !host_csr_rep_valid
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io.host.csr.resp.valid := host_csr_rep_valid
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io.host.csr.resp.bits := host_csr_bits.data
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when (io.host.csr.req.fire()) {
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host_csr_req_valid := true
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host_csr_bits := io.host.csr.req.bits
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}
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when (host_csr_req_fire) {
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host_csr_req_valid := false
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host_csr_rep_valid := true
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host_csr_bits.data := io.rw.rdata
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}
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when (io.host.csr.resp.fire()) { host_csr_rep_valid := false }
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val isa_string = "IMA" +
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(if (usingVM) "S" else "") +
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(if (usingFPU) "FDG" else "") +
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(if (usingFPU) "FD" else "") +
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(if (usingRoCC) "X" else "")
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val isa = ((if (xLen == 32) BigInt(0) else BigInt(2)) << (xLen-2)) |
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isa_string.map(x => 1 << (x - 'A')).reduce(_|_)
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@ -231,9 +210,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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CSRs.mepc -> reg_mepc.sextTo(xLen),
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CSRs.mbadaddr -> reg_mbadaddr.sextTo(xLen),
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CSRs.mcause -> reg_mcause,
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CSRs.mhartid -> io.host.id,
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CSRs.mtohost -> reg_tohost,
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CSRs.mfromhost -> reg_fromhost)
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CSRs.mhartid -> io.prci.id)
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if (usingFPU) {
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read_mapping += CSRs.fflags -> reg_fflags
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@ -295,8 +272,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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read_mapping += addr -> io.rocc.csr.rdata(i)
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}
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val addr = Mux(cpu_ren, io.rw.addr, host_csr_bits.addr)
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val decoded_addr = read_mapping map { case (k, v) => k -> (addr === k) }
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val decoded_addr = read_mapping map { case (k, v) => k -> (io.rw.addr === k) }
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val addr_valid = decoded_addr.values.reduce(_||_)
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val fp_csr =
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@ -306,11 +282,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val priv_sufficient = reg_mstatus.prv >= csr_addr_priv
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val read_only = io.rw.addr(11,10).andR
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val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R && priv_sufficient
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val wen = cpu_wen && !read_only || host_csr_req_fire && host_csr_bits.rw
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val wdata = Mux(io.rw.cmd === CSR.W, io.rw.wdata,
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val wen = cpu_wen && !read_only
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val wdata = Mux(io.rw.cmd === CSR.S, io.rw.rdata | io.rw.wdata,
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Mux(io.rw.cmd === CSR.C, io.rw.rdata & ~io.rw.wdata,
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Mux(io.rw.cmd === CSR.S, io.rw.rdata | io.rw.wdata,
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host_csr_bits.data)))
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io.rw.wdata))
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val do_system_insn = priv_sufficient && system_insn
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val opcode = UInt(1) << io.rw.addr(2,0)
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@ -397,12 +372,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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assert(PopCount(insn_ret :: io.exception :: csr_xcpt :: Nil) <= 1, "these conditions must be mutually exclusive")
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reg_mip.mtip := io.host.timerIRQ
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io.time := reg_cycle
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io.csr_stall := reg_wfi
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when (host_csr_req_fire && !host_csr_bits.rw && decoded_addr(CSRs.mtohost)) { reg_tohost := UInt(0) }
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io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
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io.fcsr_rm := reg_frm
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@ -455,8 +427,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata >> 2 << 2 }
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when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
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when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata(vaddrBitsExtended-1,0) }
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when (decoded_addr(CSRs.mfromhost)){ when (reg_fromhost === UInt(0) || !host_csr_req_fire) { reg_fromhost := wdata } }
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when (decoded_addr(CSRs.mtohost)) { when (reg_tohost === UInt(0) || host_csr_req_fire) { reg_tohost := wdata } }
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if (usingFPU) {
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when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
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when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
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@ -488,7 +458,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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}
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}
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io.rocc.csr.waddr := addr
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reg_mip := io.prci.interrupts
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io.rocc.csr.waddr := io.rw.addr
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io.rocc.csr.wdata := wdata
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io.rocc.csr.wen := wen
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}
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@ -110,7 +110,7 @@ object ImmGen {
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class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val host = new HtifIO
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val prci = new PRCICoreIO().flip
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val imem = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
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val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
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val ptw = new DatapathPTWIO().flip
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@ -426,7 +426,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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csr.io.exception := wb_reg_xcpt
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csr.io.cause := wb_reg_cause
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csr.io.retire := wb_valid
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io.host <> csr.io.host
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csr.io.prci <> io.prci
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io.fpu.fcsr_rm := csr.io.fcsr_rm
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csr.io.fcsr_flags := io.fpu.fcsr_flags
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csr.io.rocc <> io.rocc
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@ -581,7 +581,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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}
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else {
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printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
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io.host.id, csr.io.time(31,0), wb_valid, wb_reg_pc,
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io.prci.id, csr.io.time(31,0), wb_valid, wb_reg_pc,
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Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen,
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wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
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wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
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@ -30,7 +30,8 @@ abstract class Tile(resetSignal: Bool = null)
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val io = new Bundle {
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val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
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val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
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val host = new HtifIO
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val host = new HtifIO // Unused, but temporarily extant for zscale/groundtest
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val prci = new PRCICoreIO().flip
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val dma = new DmaIO
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}
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}
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@ -47,7 +48,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
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val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
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val cachedPorts = collection.mutable.ArrayBuffer(dcache.io.mem)
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io.host <> core.io.host
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core.io.prci <> io.prci
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icache.io.cpu <> core.io.imem
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val fpuOpt = if (p(UseFPU)) Some(Module(new FPU)) else None
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@ -71,7 +72,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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rocc.io.cmd <> cmdRouter.io.out(i)
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rocc.io.status := core.io.rocc.status
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rocc.io.exception := core.io.rocc.exception
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rocc.io.host_id := io.host.id
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rocc.io.host_id := io.prci.id
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dcIF.io.requestor <> rocc.io.mem
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dcPorts += dcIF.io.cache
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uncachedArbPorts += rocc.io.autl
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@ -141,4 +142,9 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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fpu.io.cp_resp.ready := Bool(false)
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}
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}
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// TODO remove
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io.host.csr.resp.valid := io.host.csr.req.valid
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io.host.csr.req.ready := io.host.csr.resp.ready
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io.host.csr.resp.bits := UInt(0)
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}
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