Specify some uninferrable widths

It's really scary that Chisel2 passed this stuff.

rocket/src/main/scala/btb.scala

@@ -177,7 +177,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
 
   val useUpdatePageHit = updatePageHit.orR
   val doIdxPageRepl = !useUpdatePageHit
-  val idxPageRepl = Wire(UInt())
+  val idxPageRepl = Wire(UInt(width = nPages))
   val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
   val idxPageUpdate = OHToUInt(idxPageUpdateOH)
   val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))

rocket/src/main/scala/icache.scala

@@ -218,7 +218,7 @@ class ICache extends FrontendModule
 
   val s1_tag_match = Wire(Vec(Bool(), nWays))
   val s2_tag_hit = Wire(Vec(Bool(), nWays))
-  val s2_dout = Reg(Vec(Bits(), nWays))
+  val s2_dout = Reg(Vec(Bits(width = code.width(rowBits)), nWays))
 
   for (i <- 0 until nWays) {
     val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool

rocket/src/main/scala/nbdcache.scala

@@ -304,7 +304,7 @@ class MSHRFile extends L1HellaCacheModule {
   when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
 
   val idxMatch = Wire(Vec(Bool(), nMSHRs))
-  val tagList = Wire(Vec(Bits(), nMSHRs))
+  val tagList = Wire(Vec(Bits(width = tagBits), nMSHRs))
   val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits
 
   val wbTagList = Wire(Vec(Bits(), nMSHRs))