1
0

Don't use clone

This commit is contained in:
Andrew Waterman 2015-07-15 17:30:50 -07:00
parent be2ff6dec7
commit 5b7f3c3006
5 changed files with 8 additions and 8 deletions

View File

@ -367,7 +367,7 @@ class Control extends CoreModule
val ex_reg_xcpt_interrupt = Reg(Bool())
val ex_reg_valid = Reg(Bool())
val ex_reg_btb_hit = Reg(Bool())
val ex_reg_btb_resp = Reg(io.imem.btb_resp.bits.clone)
val ex_reg_btb_resp = Reg(io.imem.btb_resp.bits)
val ex_reg_xcpt = Reg(Bool())
val ex_reg_flush_pipe = Reg(Bool())
val ex_reg_load_use = Reg(Bool())
@ -376,7 +376,7 @@ class Control extends CoreModule
val mem_reg_xcpt_interrupt = Reg(Bool())
val mem_reg_valid = Reg(Bool())
val mem_reg_btb_hit = Reg(Bool())
val mem_reg_btb_resp = Reg(io.imem.btb_resp.bits.clone)
val mem_reg_btb_resp = Reg(io.imem.btb_resp.bits)
val mem_reg_xcpt = Reg(Bool())
val mem_reg_replay = Reg(Bool())
val mem_reg_flush_pipe = Reg(Bool())

View File

@ -55,7 +55,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
val s2_valid = Reg(init=Bool(true))
val s2_pc = Reg(init=UInt(START_ADDR))
val s2_btb_resp_valid = Reg(init=Bool(false))
val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone)
val s2_btb_resp_bits = Reg(btb.io.resp.bits)
val s2_xcpt_if = Reg(init=Bool(false))
val msb = vaddrBits-1

View File

@ -602,19 +602,19 @@ class HellaCache extends L1HellaCacheModule {
io.cpu.req.ready := Bool(true)
val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))
val s1_req = Reg(io.cpu.req.bits.clone)
val s1_req = Reg(io.cpu.req.bits)
val s1_valid_masked = s1_valid && !io.cpu.req.bits.kill
val s1_replay = Reg(init=Bool(false))
val s1_clk_en = Reg(Bool())
val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
val s2_req = Reg(io.cpu.req.bits.clone)
val s2_req = Reg(io.cpu.req.bits)
val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
val s2_recycle = Bool()
val s2_valid_masked = Bool()
val s3_valid = Reg(init=Bool(false))
val s3_req = Reg(io.cpu.req.bits.clone)
val s3_req = Reg(io.cpu.req.bits)
val s3_way = Reg(Bits())
val s1_recycled = RegEnable(s2_recycle, Bool(false), s1_clk_en)

View File

@ -62,7 +62,7 @@ class AccumulatorExample extends RoCC
{
val n = 4
val regfile = Mem(UInt(width = xLen), n)
val busy = Reg(init=Vec.fill(n){Bool(false)})
val busy = Reg(init=Vec(Bool(false), n))
val cmd = Queue(io.cmd)
val funct = cmd.bits.inst.funct

View File

@ -109,7 +109,7 @@ class TLB extends TLBModule {
val r_req = Reg(new TLBReq)
val tag_cam = Module(new RocketCAM)
val tag_ram = Mem(io.ptw.resp.bits.pte.ppn.clone, entries)
val tag_ram = Mem(io.ptw.resp.bits.pte.ppn, entries)
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
tag_cam.io.tag := lookup_tag