Don't use clone
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be2ff6dec7
commit
5b7f3c3006
@ -367,7 +367,7 @@ class Control extends CoreModule
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val ex_reg_xcpt_interrupt = Reg(Bool())
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val ex_reg_valid = Reg(Bool())
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val ex_reg_btb_hit = Reg(Bool())
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val ex_reg_btb_resp = Reg(io.imem.btb_resp.bits.clone)
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val ex_reg_btb_resp = Reg(io.imem.btb_resp.bits)
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val ex_reg_xcpt = Reg(Bool())
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val ex_reg_flush_pipe = Reg(Bool())
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val ex_reg_load_use = Reg(Bool())
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@ -376,7 +376,7 @@ class Control extends CoreModule
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val mem_reg_xcpt_interrupt = Reg(Bool())
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val mem_reg_valid = Reg(Bool())
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val mem_reg_btb_hit = Reg(Bool())
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val mem_reg_btb_resp = Reg(io.imem.btb_resp.bits.clone)
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val mem_reg_btb_resp = Reg(io.imem.btb_resp.bits)
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val mem_reg_xcpt = Reg(Bool())
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val mem_reg_replay = Reg(Bool())
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val mem_reg_flush_pipe = Reg(Bool())
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@ -55,7 +55,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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val s2_valid = Reg(init=Bool(true))
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val s2_pc = Reg(init=UInt(START_ADDR))
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone)
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val s2_btb_resp_bits = Reg(btb.io.resp.bits)
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val s2_xcpt_if = Reg(init=Bool(false))
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val msb = vaddrBits-1
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@ -602,19 +602,19 @@ class HellaCache extends L1HellaCacheModule {
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io.cpu.req.ready := Bool(true)
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val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))
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val s1_req = Reg(io.cpu.req.bits.clone)
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val s1_req = Reg(io.cpu.req.bits)
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val s1_valid_masked = s1_valid && !io.cpu.req.bits.kill
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val s1_replay = Reg(init=Bool(false))
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val s1_clk_en = Reg(Bool())
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val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
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val s2_req = Reg(io.cpu.req.bits.clone)
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val s2_req = Reg(io.cpu.req.bits)
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val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
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val s2_recycle = Bool()
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val s2_valid_masked = Bool()
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val s3_valid = Reg(init=Bool(false))
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val s3_req = Reg(io.cpu.req.bits.clone)
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val s3_req = Reg(io.cpu.req.bits)
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val s3_way = Reg(Bits())
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val s1_recycled = RegEnable(s2_recycle, Bool(false), s1_clk_en)
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@ -62,7 +62,7 @@ class AccumulatorExample extends RoCC
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{
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val n = 4
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val regfile = Mem(UInt(width = xLen), n)
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val busy = Reg(init=Vec.fill(n){Bool(false)})
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val busy = Reg(init=Vec(Bool(false), n))
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val cmd = Queue(io.cmd)
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val funct = cmd.bits.inst.funct
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@ -109,7 +109,7 @@ class TLB extends TLBModule {
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val r_req = Reg(new TLBReq)
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val tag_cam = Module(new RocketCAM)
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val tag_ram = Mem(io.ptw.resp.bits.pte.ppn.clone, entries)
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val tag_ram = Mem(io.ptw.resp.bits.pte.ppn, entries)
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val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
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tag_cam.io.tag := lookup_tag
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