Misc. CSR fixes/improvements
- Support RV32 mstatus register - Don't ignore mstatus.stie bit - Support custom M-mode R/W CSRs for Raven chip
This commit is contained in:
Andrew Waterman
parent
822698b567
commit
90b31586ff
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@ -18,6 +18,7 @@ case object FastMulDiv extends Field[Boolean]
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case object CoreInstBits extends Field[Int]
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case object CoreDataBits extends Field[Int]
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case object CoreDCacheReqTagBits extends Field[Int]
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case object NCustomMRWCSRs extends Field[Int]
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abstract trait CoreParameters extends UsesParameters {
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val xLen = params(XLen)
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@ -11,21 +11,22 @@ import scala.math._
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class MStatus extends Bundle {
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val sd = Bool()
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val zero6 = UInt(width = 19)
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val zero4 = UInt(width = 19)
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val ha = UInt(width = 4)
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val sa = UInt(width = 4)
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val ua = UInt(width = 4)
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val zero5 = UInt(width = 1)
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val sd_rv32 = UInt(width = 1)
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val xs = UInt(width = 2)
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val fs = UInt(width = 2)
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val mtie = Bool()
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val htie = Bool()
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val stie = Bool()
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val zero4 = UInt(width = 1)
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val vm = UInt(width = 4)
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val zero3 = UInt(width = 1)
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val vm = UInt(width = 4)
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val zero2 = UInt(width = 1)
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val mprv = UInt(width = 2)
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val zero2 = UInt(width = 3)
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val prv3 = UInt(width = 2)
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val ie3 = Bool()
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val prv2 = UInt(width = 2)
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val ie2 = Bool()
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val prv1 = UInt(width = 2)
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@ -90,10 +91,10 @@ class CSRFileIO extends CoreBundle {
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val exception = Bool(INPUT)
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val retire = UInt(INPUT, log2Up(1+retireWidth))
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val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+retireWidth)))
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val custom_mrw_csrs = Vec.fill(params(NCustomMRWCSRs))(UInt(INPUT, xLen))
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val cause = UInt(INPUT, xLen)
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val mbadaddr_wen = Bool(INPUT)
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val pc = SInt(INPUT, vaddrBits+1)
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val sret = Bool(INPUT)
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val fatc = Bool(OUTPUT)
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val time = UInt(OUTPUT, xLen)
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val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
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@ -141,7 +142,7 @@ class CSRFile extends CoreModule
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}
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}
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checkInterrupt(PRV_S, r_irq_timer, 0)
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checkInterrupt(PRV_S, reg_mstatus.stie && r_irq_timer, 0)
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checkInterrupt(PRV_S, reg_mstatus.ssip, 1)
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checkInterrupt(PRV_M, reg_mstatus.msip, 1)
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checkInterrupt(PRV_M, reg_fromhost != 0, 2)
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@ -198,7 +199,6 @@ class CSRFile extends CoreModule
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CSRs.mbadaddr -> reg_mbadaddr,
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CSRs.mcause -> reg_mcause,
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CSRs.stimecmp -> reg_stimecmp,
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CSRs.stvec -> reg_stvec,
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CSRs.hartid -> io.host.id,
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CSRs.send_ipi -> io.host.id, /* don't care */
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CSRs.stats -> reg_stats,
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@ -213,11 +213,19 @@ class CSRFile extends CoreModule
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read_mapping += CSRs.sptbr -> reg_sptbr
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read_mapping += CSRs.sasid -> UInt(0)
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read_mapping += CSRs.sepc -> reg_sepc
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read_mapping += CSRs.stvec -> reg_stvec
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}
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for (i <- 0 until reg_uarch_counters.size)
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read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
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for (i <- 0 until params(NCustomMRWCSRs)) {
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val addr = 0x790 + i // turn 0x790 into parameter CustomMRWCSRBase?
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require(addr >= 0x780 && addr <= 0x7ff, "custom MRW CSR address " + i + " is out of range")
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require(!read_mapping.contains(addr), "custom MRW CSR address " + i + " is already in use")
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read_mapping += addr -> io.custom_mrw_csrs(i)
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}
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val addr = Mux(cpu_ren, io.rw.addr, host_pcr_bits.addr)
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val decoded_addr = read_mapping map { case (k, v) => k -> (addr === k) }
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@ -257,6 +265,8 @@ class CSRFile extends CoreModule
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io.status.fs := reg_mstatus.fs.orR.toSInt // either off or dirty (no clean/initial support yet)
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io.status.xs := reg_mstatus.xs.orR.toSInt // either off or dirty (no clean/initial support yet)
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io.status.sd := reg_mstatus.xs.orR || reg_mstatus.fs.orR
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if (xLen == 32)
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io.status.sd_rv32 := io.status.sd
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when (io.exception || csr_xcpt) {
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reg_mstatus.ie := false
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@ -352,7 +362,6 @@ class CSRFile extends CoreModule
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when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
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when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
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when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata }
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when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata(vaddrBits-1,0).toSInt }
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when (decoded_addr(CSRs.scycle)) { reg_time := wdata.toUInt }
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when (decoded_addr(CSRs.stime)) { reg_time := wdata.toUInt }
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when (decoded_addr(CSRs.sinstret)) { reg_instret := wdata.toUInt }
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@ -374,6 +383,7 @@ class CSRFile extends CoreModule
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when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
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when (decoded_addr(CSRs.sptbr)) { reg_sptbr := Cat(wdata(paddrBits-1, pgIdxBits), Bits(0, pgIdxBits)).toUInt }
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when (decoded_addr(CSRs.sepc)) { reg_sepc := wdata(vaddrBits,0).toSInt }
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when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata(vaddrBits-1,0).toSInt }
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}
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}
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@ -391,6 +401,8 @@ class CSRFile extends CoreModule
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reg_mstatus.prv1 := PRV_U /* hard-wired to 0 when missing user mode */
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reg_mstatus.ie2 := false
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reg_mstatus.prv2 := PRV_U /* hard-wired to 0 when missing supervisor mode */
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reg_mstatus.ie3 := false
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reg_mstatus.prv3 := PRV_U /* hard-wired to 0 when missing hypervisor mode */
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reg_mstatus.mprv := PRV_M
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reg_mstatus.zero2 := 0
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reg_mstatus.vm := 0
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@ -400,11 +412,11 @@ class CSRFile extends CoreModule
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reg_mstatus.mtie := false
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reg_mstatus.fs := 0
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reg_mstatus.xs := 0
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reg_mstatus.zero4 := 0
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reg_mstatus.sd_rv32 := false
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reg_mstatus.ua := 4
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reg_mstatus.sa := 4
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reg_mstatus.ha := 0
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reg_mstatus.zero5 := 0
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reg_mstatus.zero4 := 0
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reg_mstatus.sd := false
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}
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}
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