Fix IOMSHR state machine bug
Sending the finish too early causes the CPU response to get dropped. attn @zhemao
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@ -170,9 +170,15 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val grant_word = Reg(UInt(width = wordBits))
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val fq = Module(new FinishQueue(1))
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val s_idle :: s_acquire :: s_grant :: s_resp :: s_finish :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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io.req.ready := (state === s_idle)
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fq.io.enq.valid := io.grant.valid && io.grant.bits.requiresAck()
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fq.io.enq.bits := io.grant.bits.makeFinish()
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io.finish <> fq.io.deq
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io.finish.valid := fq.io.deq.valid && (state === s_finish)
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io.finish.bits := fq.io.deq.bits
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fq.io.deq.ready := io.finish.ready && (state === s_finish)
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val storegen = new StoreGen(req.typ, req.addr, req.data, wordBytes)
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val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc, wordBytes)
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@ -181,11 +187,6 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
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val beat_data = Fill(beatWords, storegen.data)
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val s_idle :: s_acquire :: s_grant :: s_resp :: s_finish :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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io.req.ready := (state === s_idle)
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val addr_block = req.addr(paddrBits - 1, blockOffBits)
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val addr_beat = req.addr(blockOffBits - 1, beatOffBits)
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val addr_byte = req.addr(beatOffBits - 1, 0)
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