79b53cf2ae
Add dip switches and clean up top interface
2018-05-01 00:07:58 +02:00
5bcc4e82fd
Generate separate processor and terminal clocks
2018-04-30 22:52:02 +02:00
9c06418352
Add terminal/dvi io (unsing the same clock for now)
2018-04-30 00:41:05 +02:00
b2b19cc822
Add clock and proper reset feedback to ml507
2018-04-19 01:29:15 +02:00
5db71d11c2
Fix polarity of buttons and dips on the ml507
2018-04-19 01:28:36 +02:00
f4ae1d469f
Remove unused signals (pcie, mem) from ml507 shell
2018-04-19 01:27:35 +02:00
0b421d5645
Remove incorrect jtag pin constraints form ml507
2018-04-19 01:26:15 +02:00
8329b232e2
Hold ml507 in reset while clock not locked
2018-04-19 01:25:31 +02:00
2ff28e6af6
Add status indication led for the reset button
2018-04-18 00:26:43 +02:00
41362a1cb5
Remove unused UART signals (rs and cs) from ml507
2018-04-18 00:26:00 +02:00
e9625bf8ee
Add initial ML507Shell stub based on VC707Shell
2018-04-12 00:42:46 +02:00
Wesley W. Terpstra
9d02f530fc
vc707shell: work-around too many '++'s => stack overflow issue
2018-03-22 18:08:32 -07:00
Wesley W. Terpstra
080119ec7a
chiplink: add pinout ( #20 )
2018-03-22 17:13:25 -07:00
Henry Cook
0ca9f2bb66
periphery: bus api update ( #17 )
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* periphery: bus api update
* Update XilinxVC707MIGPeriphery.scala
2018-03-01 01:16:04 -08:00
Wesley W. Terpstra
1dda525578
prologue: support the absence of an xdc/tcl constraint file
2018-02-25 15:21:03 -08:00
Wesley W. Terpstra
6df6db25de
Merge pull request #18 from sifive/dynamic-clock-groups
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Dynamic clock groups -- fixes timing closure problem for vc707 designs without ChipLink
2018-02-25 15:08:15 -08:00
Wesley W. Terpstra
4386187016
vc707: add clock groups dynamically iff they exist
2018-02-25 14:33:32 -08:00
Wesley W. Terpstra
b7afc83a34
xilinx prologue: support tcl for constraints
2018-02-25 14:32:39 -08:00
Wesley W. Terpstra
17e13a3a50
Merge pull request #16 from sifive/chiplink-100
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Chiplink 100
2018-02-08 15:40:16 -08:00
Wesley W. Terpstra
8519ba8d4e
vc707: setup 100MHz PLL
2018-02-08 07:21:45 -08:00
Wesley W. Terpstra
506d2da883
vc707: update constraints to match correct mmcm
2018-02-08 07:21:45 -08:00
Wesley W. Terpstra
9c38f20333
vc707 axi: move addresses to line up with ChipLink
2018-02-08 07:21:44 -08:00
Henry Styles
61ece0bf00
VC707 Shell : additional skewed clocks
2018-02-08 07:21:44 -08:00
Henry Styles
0fdbb778bf
VC707 Shell : move DebugJTAG pins and connect function into a separate mix-in
2018-02-08 07:21:44 -08:00
Henry Styles
045b290fbd
VC707 JTAG support throught XM105 FMC or reuse of LCD header
2018-02-08 07:21:44 -08:00
Henry Styles
f9dc552ddc
Xilinx unisim typo
2018-02-08 07:21:44 -08:00
Henry Styles
33c88b8cc4
Move Xilinx unisims into separate file
2018-02-08 07:21:44 -08:00
Wesley W. Terpstra
8b0d7ec91a
TransferSizes: just because a device CAN do more does not mean it should ( #15 )
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Capping TransferSizes at 128 fits nicely in 3 size bits.
2017-12-10 00:42:11 -08:00
Henry Styles
ba7beb676d
Merge pull request #14 from sifive/vc707_mig_pcie_traits
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VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits
2017-11-01 16:58:44 -07:00
Henry Styles
e1bfb75188
VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock
2017-11-01 14:23:07 -07:00
Wesley W. Terpstra
df8e6b8e8c
xilinxvc707pciex1: use new node-style API and abstract crossing ( #13 )
2017-10-28 12:27:24 -07:00
Wesley W. Terpstra
65ac5d4588
xilinxVC707mig: convert to the island pattern ( #12 )
2017-10-26 16:38:52 -07:00
Henry Styles
eaf1c3ed54
Merge pull request #11 from sifive/vc707_use_ip_io_bundles
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VC707 use IP IO bundles
2017-10-24 17:49:31 -07:00
Henry Styles
dc6bb40d1b
VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP
2017-10-23 17:27:36 -07:00
Henry Styles
61b167e8d9
VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals
2017-10-23 16:53:59 -07:00
Wesley W. Terpstra
d8e50c7646
TLToAXI4: remove now unnecessary argument ( #10 )
2017-10-12 14:37:21 -07:00
Richard Xia
66e5ac2e9e
Merge pull request #8 from sifive/replace-env-vars-with-cli-args
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Restructure Tcl script entrypoint.
2017-10-04 14:28:10 -07:00
Richard Xia
9593e5eee6
Restructure Tcl script entrypoint.
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vivado.tcl is now the entrypoint for the Vivado Tcl scripts and will
automatically source all the other required scripts.
A command line argument parser was written and replaces the previous system of
using environment variables to pass values into the scripts. The VSRCSVIVADOTCL
environment variable has been replaced with a -F command line option, and the
file format has changed from a Tcl script to a simple newline-delimited list of
files.
2017-10-04 14:15:39 -07:00
Wesley W. Terpstra
4af0552374
diplomacy: update to new API ( #7 )
2017-09-27 16:32:43 -07:00
Megan Wachs
32d4083890
Merge pull request #6 from sifive/signal_bundles
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signal_bundles: Use the new way as .fromPorts is gone
2017-09-25 11:20:44 -07:00
Megan Wachs
bf48e2c7c4
signal_bundles: Use the new way as .fromPorts is gone
2017-09-22 13:31:11 -07:00
Henry Styles
e9019d7570
Merge pull request #5 from sifive/vivado_vsrcs_using_file
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Use a file instead of environment variable to pass VSRCS into Vivado
2017-09-19 14:13:36 -07:00
Henry Styles
97e628639a
Use a file instead of environment variable to pass VSRCS into Vivado
2017-09-19 14:12:23 -07:00
Henry Styles
2bed0c30dc
correct invoke of board specific ip.tcl
2017-09-08 23:20:55 -07:00
Henry Styles
07b2ae07d2
Merge pull request #4 from sifive/vc707_2GB
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Support both 4G and 1GB DIMM configuration for VC707
2017-09-08 16:09:18 -07:00
Henry Styles
9f75e6eb59
Support both 4G and 1GB DIMM configuration for VC707
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Generate IP TCL and MIG projects from the Chisel blackboxes
2017-09-08 15:52:53 -07:00
Megan Wachs
e49f49686d
Merge pull request #1 from sifive/synchronizers
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synchronizers: Use new primitives
2017-09-07 13:33:26 -07:00
Megan Wachs
31650a2d23
Merge remote-tracking branch 'origin/master' into synchronizers
2017-09-07 10:46:03 -07:00
Henry Styles
385ffa7d9a
Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc
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fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
2017-09-07 10:42:32 -07:00
Henry Styles
b7ee0ab0f0
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
2017-09-07 10:41:12 -07:00
