vc707: setup 100MHz PLL
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506d2da883
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8519ba8d4e
@ -243,7 +243,7 @@ class vc707_sys_clock_mmcm2 extends BlackBox {
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CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \
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CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {100} \
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CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {150.000} \
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CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {12.5} \
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CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {100} \
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CONFIG.CLKOUT7_REQUESTED_PHASE {180} \
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CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
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CONFIG.PRIM_IN_FREQ {200.000} \
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@ -257,22 +257,22 @@ class vc707_sys_clock_mmcm2 extends BlackBox {
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CONFIG.MMCM_CLKOUT3_DIVIDE {18} \
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CONFIG.MMCM_CLKOUT4_DIVIDE {9} \
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CONFIG.MMCM_CLKOUT5_DIVIDE {6} \
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CONFIG.MMCM_CLKOUT6_DIVIDE {72} \
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CONFIG.MMCM_CLKOUT6_DIVIDE {9} \
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CONFIG.NUM_OUT_CLKS {7} \
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CONFIG.CLKOUT1_JITTER {206.010} \
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CONFIG.CLKOUT1_PHASE_ERROR {105.461} \
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CONFIG.CLKOUT2_JITTER {180.172} \
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CONFIG.CLKOUT2_PHASE_ERROR {105.461} \
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CONFIG.CLKOUT3_JITTER {166.503} \
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CONFIG.CLKOUT3_PHASE_ERROR {105.503} \
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CONFIG.CLKOUT3_PHASE_ERROR {105.461} \
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CONFIG.CLKOUT4_JITTER {157.199} \
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CONFIG.CLKOUT4_PHASE_ERROR {105.461} \
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CONFIG.CLKOUT5_JITTER {110.629} \
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CONFIG.CLKOUT5_PHASE_ERROR {136.686} \
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CONFIG.CLKOUT5_JITTER {136.686} \
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CONFIG.CLKOUT5_PHASE_ERROR {105.461} \
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CONFIG.CLKOUT6_JITTER {126.399} \
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CONFIG.CLKOUT6_PHASE_ERROR {105.461} \
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CONFIG.CLKOUT7_JITTER {206.010} \
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CONFIG.CLKOUT7_PHASE_ERROR {105.461}] [get_ips vc707_sys_clock_mmcm2] """
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CONFIG.CLKOUT7_PHASE_ERROR {136.686}] [get_ips vc707_sys_clock_mmcm2] """
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)
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}
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@ -280,31 +280,29 @@ class vc707_sys_clock_mmcm3 extends BlackBox {
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val io = new Bundle {
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val clk_in1 = Bool(INPUT)
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val clk_out1 = Clock(OUTPUT)
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val clk_out2 = Clock(OUTPUT)
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val reset = Bool(INPUT)
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val locked = Bool(OUTPUT)
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}
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ElaborationArtefacts.add(
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"vc707_sys_clock_mmcm3.vivado.tcl",
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"""create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name vc707_sys_clock_mmcm3 -dir $ipdir -force
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set_property -dict [list CONFIG.PRIM_IN_FREQ {12.5} \
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CONFIG.CLKOUT2_USED {true} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.5} \
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CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {12.5} \
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CONFIG.CLKOUT2_REQUESTED_PHASE {180} \
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CONFIG.CLKIN1_JITTER_PS {800.0} \
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CONFIG.MMCM_DIVCLK_DIVIDE {1} \
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CONFIG.MMCM_CLKFBOUT_MULT_F {64.000} \
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CONFIG.MMCM_CLKIN1_PERIOD {80.0} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {64.000} \
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CONFIG.MMCM_CLKOUT1_DIVIDE {64} \
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CONFIG.MMCM_CLKOUT1_PHASE {180.000} \
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CONFIG.NUM_OUT_CLKS {2} \
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CONFIG.CLKOUT1_JITTER {627.393} \
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CONFIG.CLKOUT1_PHASE_ERROR {651.718} \
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CONFIG.CLKOUT2_JITTER {627.393} \
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CONFIG.CLKOUT2_PHASE_ERROR {651.718}] [get_ips vc707_sys_clock_mmcm3] """
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set_property -dict [list \
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CONFIG.PRIM_SOURCE {No_buffer} \
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CONFIG.PRIM_IN_FREQ {100} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100} \
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CONFIG.CLKOUT1_REQUESTED_PHASE {180} \
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CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
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CONFIG.CLKIN1_JITTER_PS {100.0} \
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CONFIG.MMCM_DIVCLK_DIVIDE {1} \
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CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \
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CONFIG.MMCM_CLKIN1_PERIOD {10.0} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} \
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CONFIG.MMCM_CLKOUT1_DIVIDE {10} \
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CONFIG.MMCM_CLKOUT1_PHASE {180.000} \
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CONFIG.NUM_OUT_CLKS {1} \
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CONFIG.CLKOUT1_JITTER {130.958} \
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CONFIG.CLKOUT1_PHASE_ERROR {98.575}] [get_ips vc707_sys_clock_mmcm3] """
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)
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}
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@ -233,7 +233,7 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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val clk100 = vc707_sys_clock_mmcm0.io.clk_out5
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val clk150 = vc707_sys_clock_mmcm0.io.clk_out6
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val clk75 = vc707_sys_clock_mmcm0.io.clk_out7
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val clk12_5_180 = vc707_sys_clock_mmcm0.io.clk_out7
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val clk100_180 = vc707_sys_clock_mmcm0.io.clk_out7
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val vc707_sys_clock_mmcm0_locked = vc707_sys_clock_mmcm0.io.locked
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//65MHz and multiples
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@ -72,9 +72,12 @@ set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRU
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set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}]
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set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}]
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create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk]
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set_clock_groups -asynchronous \
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-group { clk_pll_i } \
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-group { \
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sys_diff_clk \
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clk_out1_vc707_sys_clock_mmcm2 \
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clk_out2_vc707_sys_clock_mmcm2 \
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clk_out3_vc707_sys_clock_mmcm2 \
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@ -85,5 +88,7 @@ set_clock_groups -asynchronous \
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-group { \
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clk_out1_vc707_sys_clock_mmcm1 \
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clk_out2_vc707_sys_clock_mmcm1 } \
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-group { \
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clk_out1_vc707_sys_clock_mmcm3 \
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chiplink_b2c_clock } \
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-group [list [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]]
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