riscv/fpga-shells
1
0
Fork 0
Code Releases Activity
Freedom FPGA mappings (https://github.com/sifive/fpga-shells)
16 Commits 2 Branches 0 Tags 682 KiB
Scala 89.5%
Tcl 7.8%
Verilog 2%
Makefile 0.7%
97e628639a
Go to file
Henry Styles 97e628639a Use a file instead of environment variable to pass VSRCS into Vivado
2017-09-19 14:12:23 -07:00
src/main/scala Support both 4G and 1GB DIMM configuration for VC707 2017-09-08 15:52:53 -07:00
xilinx Use a file instead of environment variable to pass VSRCS into Vivado 2017-09-19 14:12:23 -07:00
.gitignore Initial commit for fpga-shells 2017-08-16 11:23:45 -07:00